GitHub topics: chisel3

Repositories

chipsalliance/chisel

Chisel: A Modern Hardware Design Language

Language: Scala - Size: 138 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 4,262 - Forks: 623

enkerewpo/methane

A polyphonic synthesizer built on fpga and esp32

Language: SystemVerilog - Size: 67.5 MB - Last synced at: 6 days ago - Pushed at: over 1 year ago - Stars: 12 - Forks: 1

agile-hw/hw5

HW5 for Agile Hardware Design

Language: Scala - Size: 20.5 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 1

agile-hw/lectures

Lectures for the Agile Hardware Design course in Jupyter Notebooks

Language: Jupyter Notebook - Size: 2.64 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 92 - Forks: 24

agile-hw/labs

Lab assignments for the Agile Hardware Design course

Language: Jupyter Notebook - Size: 146 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 14 - Forks: 7

agile-hw/hw4

HW4 for Agile Hardware Design

Language: Scala - Size: 27.3 KB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 1 - Forks: 1

thoughtworks/hardposit-chisel3

Chisel library for Unum Type-III Posit Arithmetic

Language: C++ - Size: 4.31 MB - Last synced at: 4 days ago - Pushed at: about 1 month ago - Stars: 38 - Forks: 10

CodingPlatelets/transformer_MM

Accelerator for LLM Based on Chisel3

Language: Scala - Size: 1.34 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 10 - Forks: 0

nhynes/chisel3-axi

Chisel3 AXI4-{Lite, Full, Stream} Definitions

Language: Scala - Size: 15.6 KB - Last synced at: 7 days ago - Pushed at: over 6 years ago - Stars: 15 - Forks: 4

agile-hw/hw3

HW3 for Agile Hardware Design

Language: Scala - Size: 616 KB - Last synced at: 22 days ago - Pushed at: 22 days ago - Stars: 1 - Forks: 0

SingularityKChen/dl_accelerator

Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions

Language: Scala - Size: 5.78 MB - Last synced at: 20 days ago - Pushed at: almost 5 years ago - Stars: 189 - Forks: 32

agile-hw/hw2

HW2 for Agile Hardware Design

Language: Scala - Size: 374 KB - Last synced at: 29 days ago - Pushed at: 29 days ago - Stars: 0 - Forks: 5

rhysd/riscv32-cpu-chisel

Learning how to make RISC-V 32bit CPU with Chisel

Language: Scala - Size: 143 KB - Last synced at: 26 days ago - Pushed at: over 3 years ago - Stars: 66 - Forks: 4

freechipsproject/diagrammer

Provides dot visualizations of chisel/firrtl circuits

Language: Scala - Size: 270 KB - Last synced at: 24 days ago - Pushed at: about 2 years ago - Stars: 119 - Forks: 20

mpskex/chisel-npu

Chisel implementation of Neural Processing Unit for System on the Chip

Language: Scala - Size: 691 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 21 - Forks: 4

horie-t/TD4-with-Chisel

TD4をChiselで実装してみる

Language: Scala - Size: 25.4 KB - Last synced at: 7 days ago - Pushed at: over 4 years ago - Stars: 8 - Forks: 2

OpenXiangShan/OpenNCB

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

Language: Scala - Size: 360 KB - Last synced at: 19 days ago - Pushed at: about 2 months ago - Stars: 3 - Forks: 0

RISMicroDevices/OpenNCB 📦

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

Language: Scala - Size: 329 KB - Last synced at: 3 days ago - Pushed at: 7 months ago - Stars: 9 - Forks: 1

biggsbenjamin/ATHEENA

ATHEENA respository (including software and hardware artifacts for FCCM submission 2023)

Language: Python - Size: 11.7 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 3 - Forks: 1

LoveLonelyTime/Bergamot

An exquisite superscalar RV32GC processor.

Language: Scala - Size: 876 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 147 - Forks: 13

Shiritai/aias-lab4-spring-2024

Lab4 of AI computing Architecture and System (2024 spring) around basic chisel design

Language: Scala - Size: 31.3 KB - Last synced at: about 2 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

jiaaom/HPDLA

Systolic-array based Deep Learning Accelerator generator

Language: Verilog - Size: 32.2 KB - Last synced at: 2 months ago - Pushed at: over 4 years ago - Stars: 25 - Forks: 5

ekiwi/pynq

PYNQ with Chisel and Rust

Language: Tcl - Size: 235 KB - Last synced at: about 1 month ago - Pushed at: over 7 years ago - Stars: 25 - Forks: 4

jiegec/fpu-wrappers

Wrappers for open source FPU hardware implementations.

Language: Verilog - Size: 2.3 MB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 30 - Forks: 4

yasnakateb/ChipyardIntegration

😱 RoCC Accelerator Integration with Chipyard

Size: 8.79 KB - Last synced at: 26 days ago - Pushed at: 6 months ago - Stars: 3 - Forks: 0

EndlessKn0t/SChipper

BTech Project repository by Shreevatsa. WIP.

Language: Scheme - Size: 27.3 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

horie-t/homemade-riscv-en

Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"

Language: Scala - Size: 104 KB - Last synced at: 7 days ago - Pushed at: almost 6 years ago - Stars: 17 - Forks: 13

merledu/caravan

A caravan equipped with API for creating bus protocols in Chisel with ease.

Language: Scala - Size: 820 KB - Last synced at: 20 days ago - Pushed at: about 2 months ago - Stars: 14 - Forks: 11

howardlau1999/yatcpu

Yet another toy CPU.

Language: Scala - Size: 536 KB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 85 - Forks: 13

SinaKarvandi/FPGA

Random FPGA Projects

Language: VHDL - Size: 7.54 MB - Last synced at: 2 months ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 1

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Language: VHDL - Size: 46.9 KB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 2

buhe/study_fpga

💾 fpga study with open source tools (on macos)

Language: Scala - Size: 3.31 MB - Last synced at: about 1 month ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 0

doofin/dependentChisel

Chisel on Scala 3 with improved bit width inference

Language: Scala - Size: 688 KB - Last synced at: 5 days ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0

NakajoLab/B4SMT

Language: Scala - Size: 2.33 MB - Last synced at: 5 days ago - Pushed at: 7 months ago - Stars: 0 - Forks: 5

A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code to values dumped by simulators is now possible thanks to Tywaves!

Language: Scala - Size: 15.1 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 18 - Forks: 0

Origami404/MiniRV-Chisel

2023 年学校 CPU 设计课程作业, 一个使用 Chisel 编写的简单 RV32I CPU 核心

Language: Scala - Size: 4.36 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 0

grebe/ofdm

Chisel Things for OFDM

Language: Scala - Size: 79.4 MB - Last synced at: about 1 month ago - Pushed at: almost 5 years ago - Stars: 30 - Forks: 8

microdynamics-cpu/tree-core-ide

:deciduous_tree: The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Language: JavaScript - Size: 1.67 MB - Last synced at: 9 months ago - Pushed at: over 2 years ago - Stars: 98 - Forks: 14

yasnakateb/CGRAs

Coarse Grained Reconfigurable Arrays with Chisel3

Language: Scala - Size: 3.03 MB - Last synced at: about 1 month ago - Pushed at: 10 months ago - Stars: 12 - Forks: 0

Shiritai/aias-lab5-spring-2024

Lab5 of AI computing Architecture and System (2024 spring) around advanced chisel design of FSM (e.g. `RobustCalculator`)

Language: Scala - Size: 93.8 KB - Last synced at: about 2 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

lbnlcomputerarch/vte

Verilator Testbench Environment

Language: C++ - Size: 131 KB - Last synced at: 6 months ago - Pushed at: about 6 years ago - Stars: 3 - Forks: 1

horie-t/homemade-riscv

『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ

Language: Scala - Size: 83 KB - Last synced at: 7 days ago - Pushed at: almost 6 years ago - Stars: 13 - Forks: 4

VMois/LSM-Compactron3000

FPGA-based accelerator for compactions in LSM-tree based KV stores. Making compaction great again, again!

Language: C - Size: 3.33 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 1

SYSU-SCC/yatcpu-docs

Documentation for YatCPU

Size: 16.5 MB - Last synced at: 12 months ago - Pushed at: over 1 year ago - Stars: 45 - Forks: 11

merledu/magma-si

Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL

Language: Scala - Size: 46.8 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 8 - Forks: 3

CMU-SAFARI/Pythia-HDL

Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, please read the paper that appeared in MICRO 2021 by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

Language: Scala - Size: 753 KB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 11 - Forks: 3

indyscala/chisel3 Fork of chipsalliance/chisel-template

Hardware Construction with FPGAs and Chisel by @bfritz for Jan 2019

Language: Scala - Size: 4.35 MB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0

jiegec/fpnew-wrapper

A chisel3 wrapper for pulp-platform/fpnew

Language: SystemVerilog - Size: 83 KB - Last synced at: about 1 month ago - Pushed at: about 5 years ago - Stars: 8 - Forks: 0

meton-robean/Vector_MulAdd_Accelerator

vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器

Language: Scala - Size: 3.65 MB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 46 - Forks: 12

samadpls/ALEPH

Aleph is a single cycle processor that carries out one instruction in a single clock cycle

Language: Scala - Size: 37.2 MB - Last synced at: about 1 month ago - Pushed at: almost 2 years ago - Stars: 6 - Forks: 0

ryanlorica/processing-engine

A Scala w/ Chisel based implementation of a processing engine generator for neural network accelerators.

Language: Jupyter Notebook - Size: 947 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 10 - Forks: 1

whutddk/Rift2Core

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

Language: Scala - Size: 9.01 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 30 - Forks: 9

InternetUnexplorer/icestick-blinky

A simple demo that blinks an LED on the Lattice iCEstick Evaluation Kit, written in Chisel

Language: Scala - Size: 4.88 KB - Last synced at: 6 days ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

merledu/buraq_mini

This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

Language: Scala - Size: 1.79 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 8 - Forks: 6

karthik-r-rao/neural-net-chisel

Implementation of a Neural Network in Chisel.

Language: Verilog - Size: 171 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

merledu/100DaysOfCHISEL

100 Days of CHISEL inspired by 100DaysOfRTL

Language: Scala - Size: 1.46 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 16

SingularityKChen/NUCPU

A toy in-order RV64I CPU.

Language: Scala - Size: 226 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 6 - Forks: 2

diohabara/chisel_riscv

RISC-V CPU Core

Language: Scala - Size: 165 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

shino-hinaduki/chisel-nes

(WIP) NES emulator running on FPGA implemented in scala(w/ chisel)

Language: Verilog - Size: 8.15 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

Create-a-Second-Earth-2030/implement-CPU-with-chisel3

Size: 11.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Bindless-Chicken/chisel-blinky

Boilerplate for a full project with chisel and a DE0 Nano

Language: Scala - Size: 7.81 KB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

ryanlorica/processing-element

A configurable processing element for deep neural network accelerators

Language: Scala - Size: 1.47 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 10 - Forks: 0

josh14668/Easier-Parallel-Design-Framework

A interpreter/compiler written in python that auto-connects hardware modules written Chisel HDL and allows for easy parametrised parallelism

Language: Python - Size: 33.2 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

AlexMontgomerie/huffman-chisel

A Chisel implementation of Huffman coding for a static code table

Language: Scala - Size: 43.9 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 0

substate-tech/ambel

AMBEL is a Chisel library for generating AMBA components

Language: Scala - Size: 2.43 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 4 - Forks: 1

Starrynightzyq/soNN

A Reconﬁgurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.

Language: Verilog - Size: 12.6 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 18 - Forks: 5

char-fish-after-lunch/SystemOnCat

An SoC with multiple RISC-V IMA processors.

Language: Scala - Size: 354 KB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 19 - Forks: 5

atrosinenko/composite-video-generator

Example of composite video generation with Chisel (B/W for now)

Language: Verilog - Size: 90.8 KB - Last synced at: 11 months ago - Pushed at: almost 7 years ago - Stars: 4 - Forks: 0

AlexMontgomerie/rle-chisel

A Chisel implementation of single-value Run Length Encoding (RLE)

Language: Scala - Size: 25.4 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

panda5mt/KyogenRV

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Language: Scala - Size: 19.6 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 39 - Forks: 3

librecores/riscv-sodor Fork of ucb-bar/riscv-sodor

educational microarchitectures for risc-v isa

Language: Scala - Size: 7.58 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 60 - Forks: 20

Wonicon/VerilogBlackBox

Convert Verilog module to chisel3 BlackBox

Language: ANTLR - Size: 35.2 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 1

t1ch/shanu

FPGA implementation of the eNodeB and gNB physical layers

Language: Scala - Size: 43.9 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 6 - Forks: 0

Coekjan/MIPS-CPU 📦

MIPS CPU Constructed By Chisel 3.

Size: 34.2 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

chisel3 111 scala 36 chisel 33 fpga 23 risc-v 16 verilog 15 riscv 10 firrtl 7 rtl 7 cpu 7 hdl 7 sbt 6 agile-hardware 6 chisel-generator 5 hardware-acceleration 5 axi4 5 verilator 5 hardware 5 processor 5 soc 4 computer-architecture 4 mips 4 vivado 3 vhdl 3 accelerator 3 amba 3 fpu 3 vitis 2 asic 2 asic-design 2 waveform 2 chisel-test 2 accelerators 2 python 2 microcomputer 2 machine-learning 2 chip-generator 2 systemverilog 2 jupyter 2 floating-point 2 tilelink 2 verilog-hdl 2 amba-axi 2 protocol-bridge 2 bus 2 amba-chi 2 de0-nano 1 compression 1 comressor 1 nes-emulator 1 ahb-lite 1 asic-verification 1 kicad 1 rle 1 fgpa 1 rv32i 1 open-source-hardware 1 de0-cv 1 singularity 1 swerv 1 swerv-el2 1 mipsel 1 riscv64i 1 css 1 notebook 1 risc-processor 1 riscv32 1 intel 1 arty 1 librecores 1 pynq-z1 1 antlr4 1 code-transformation 1 5g 1 nn 1 bladerf 1 avalon-mm 1 cnn 1 lte 1 acclerometer 1 physical-layer 1 radio 1 sdr 1 apb 1 huffman-coding 1 mips-architecture 1 deep-learning 1 altera 1 mips-assembly 1 examples 1 differential-testing 1 noop 1 uncore 1 aes 1 cryptography 1 orangecrab 1 tinyfpga 1 cpu-model 1 microarchitecture 1 docker-image 1