GitHub topics: verilator
HEP-SoC/SoCMake
CMake based hardware build system
Language: CMake - Size: 6.11 MB - Last synced at: about 2 hours ago - Pushed at: about 3 hours ago - Stars: 26 - Forks: 3
Cheetos19/EDA
Exploratory Data Analysis
Language: Jupyter Notebook - Size: 26.5 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0
RDSik/axis-uart
AXI-Stream UART module
Language: SystemVerilog - Size: 246 KB - Last synced at: about 17 hours ago - Pushed at: about 17 hours ago - Stars: 1 - Forks: 0
ethanuppal/marlin
🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
Language: Rust - Size: 2.54 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 48 - Forks: 4
verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
Language: C++ - Size: 59.5 MB - Last synced at: 6 days ago - Pushed at: 7 days ago - Stars: 2,930 - Forks: 670
fjpolo/FPGA_Project-Creator
FPGA template project creator
Language: F# - Size: 6.34 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0
chili-chips-ba/wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
Language: VHDL - Size: 1.92 GB - Last synced at: 8 days ago - Pushed at: 9 days ago - Stars: 100 - Forks: 2
dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Language: Verilog - Size: 1.01 MB - Last synced at: 7 days ago - Pushed at: about 1 year ago - Stars: 349 - Forks: 83
CT7-labs/argon-cpu
16-bit CPU written in Verilog
Language: Verilog - Size: 128 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 0 - Forks: 0
mshr-h/vscode-verilog-hdl-support
HDL support for VS Code
Language: TypeScript - Size: 2.25 MB - Last synced at: 6 days ago - Pushed at: 8 days ago - Stars: 324 - Forks: 81
chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
Language: SystemVerilog - Size: 39.3 MB - Last synced at: 8 days ago - Pushed at: 9 days ago - Stars: 278 - Forks: 84
WilliamZhang20/Digital-Hardware-Blocks
Fundamental Digital Logic Concepts in Verilog
Language: Verilog - Size: 21.5 KB - Last synced at: 16 days ago - Pushed at: 17 days ago - Stars: 0 - Forks: 0
dau-dev/verilator-python
Python/PyPI wrapper for Verilator
Language: Python - Size: 54.7 KB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 2 - Forks: 0
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
Language: Verilog - Size: 2.98 MB - Last synced at: 18 days ago - Pushed at: over 3 years ago - Stars: 1,021 - Forks: 171
olofk/edalize
An abstraction library for interfacing EDA tools
Language: Python - Size: 1.08 MB - Last synced at: 21 days ago - Pushed at: about 1 month ago - Stars: 687 - Forks: 201
yangm2/verilator-example
Example of using various technologies together in a Verilator simulation
Language: Rust - Size: 44.9 KB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 4 - Forks: 1
ZipCPU/vgasim
A Video display simulator
Language: Verilog - Size: 3.82 MB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 167 - Forks: 21
XhovaniM8/MIPS-FPGA
a single-cycle 16-bit MIPS processor using SystemVerilog, simulated using Verilator.
Language: SystemVerilog - Size: 2.93 KB - Last synced at: 28 days ago - Pushed at: 28 days ago - Stars: 0 - Forks: 0
verilator/verilator_ext_tests
Extended and external tests for Verilator testing
Language: SystemVerilog - Size: 172 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 16 - Forks: 9
dominiksalvet/super-riscv
Superscalar dual-issue RISC-V processor
Language: SystemVerilog - Size: 1.78 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 7 - Forks: 3
Nambers/MIPS64
[WIP] 5-stage pipeline MIPS64 SoC implementation with peripheral components, simulated with verilator
Language: SystemVerilog - Size: 885 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
dpretet/svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Language: Python - Size: 755 KB - Last synced at: 23 days ago - Pushed at: 8 months ago - Stars: 78 - Forks: 17
MaxXSoft/Bossa
BOOM's Simulation Accelerator.
Language: Scala - Size: 104 KB - Last synced at: 8 days ago - Pushed at: over 3 years ago - Stars: 14 - Forks: 2
ZipCPU/sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Language: Verilog - Size: 15.1 MB - Last synced at: about 2 months ago - Pushed at: 5 months ago - Stars: 273 - Forks: 43
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
Language: SystemVerilog - Size: 17.6 MB - Last synced at: about 2 months ago - Pushed at: about 2 years ago - Stars: 870 - Forks: 227
ZipCPU/wbscope
A wishbone controlled scope for FPGA's
Language: Verilog - Size: 758 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 80 - Forks: 6
miree/gvi
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
Language: C++ - Size: 239 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 11 - Forks: 1
VisorFolks/cyanforge
An open source utility to build and simulate cores.
Language: Makefile - Size: 16.6 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 2 - Forks: 0
poucotm/SublimeLinter-contrib-verilator
👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)
Language: Python - Size: 88.9 KB - Last synced at: 2 months ago - Pushed at: 12 months ago - Stars: 16 - Forks: 6
klimatt/arty_a7
A playground with various modules, written in SystemVerilog, with a project setup to simplify working routines.
Language: SystemVerilog - Size: 27.7 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0
tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Language: SystemVerilog - Size: 820 KB - Last synced at: about 2 months ago - Pushed at: over 5 years ago - Stars: 275 - Forks: 60
weisrc/nesv
NESystem Verilog
Language: SystemVerilog - Size: 1.11 MB - Last synced at: 6 days ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0
Sudarshan0102/v
v is a lightweight, fast-paced text editor designed for Unix-like operating systems. It features a unique modal editing style and a powerful plugin system for customization.
Size: 0 Bytes - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0
ZipCPU/website
The ZipCPU blog
Language: HTML - Size: 187 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 15 - Forks: 8
ShaheerSajid/PakFPU
Fully synthesizable and paramterizable, IEEE-754 compliant Floating Point Unit (FPU) in systemverilog. Supports fused multiply add, division and square root operations.
Language: SystemVerilog - Size: 3.52 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 1
rehanmq/asic-soc-ml-accelerator-verification
End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.
Language: Verilog - Size: 7.81 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
ultraembedded/riscv
RISC-V CPU Core (RV32IM)
Language: Verilog - Size: 5.27 MB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 1,398 - Forks: 251
VicoHBB/Verilator-SV-Template
This project template is designed to streamline the development of SystemVerilog projects using Verilator, GTKWave, and Make. The template includes a Makefile with various recipes for compiling, simulating, and visualizing the design. It also includes a directory structure for organizing the HDL files, test benches, and simulation waveforms.
Language: SystemVerilog - Size: 62.5 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0
Abdelrahman1810/ALU-testbench-verilator
This repository provides a Verilator-based testbench for an ALU (Arithmetic Logic Unit), using VPW library (Verilator Python Wrapper). It includes a Python testbench that verifies various ALU operations.
Language: Python - Size: 10 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
Samulix20/GaZmusino
A tiny, open-source RISC-V processor designed for learning and experimentation.
Language: Assembly - Size: 39.1 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
gtavasoli/RISC-V-Lab
RISC-V Lab aims to provide a hands-on experience in working with the RISC-V BOOM core, running simulations, and testing various security aspects.
Size: 8.79 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0
JasonBrave/pci-edu
SystemVerilog implemention of QEMU PCI edu device
Language: SystemVerilog - Size: 56.6 KB - Last synced at: 2 months ago - Pushed at: about 2 years ago - Stars: 11 - Forks: 2
ultraembedded/cores
Various HDL (Verilog) IP Cores
Language: Verilog - Size: 211 KB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 745 - Forks: 218
sgherbst/svreal
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
Language: SystemVerilog - Size: 253 KB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 44 - Forks: 8
Risto97/pygears-uvm
SystemC UVM environment generator for PyGears components. RTL simulated with Verilator
Language: C++ - Size: 69.3 KB - Last synced at: 2 months ago - Pushed at: over 5 years ago - Stars: 6 - Forks: 3
wyvernSemi/mem_model
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
Language: VHDL - Size: 2.71 MB - Last synced at: 2 months ago - Pushed at: 7 months ago - Stars: 22 - Forks: 3
arhamhashmi01/rv32i-pipeline-processor
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
Language: Verilog - Size: 357 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 10 - Forks: 0
djg/cpu
CPU - Verilog + Rust
Language: CMake - Size: 14.6 KB - Last synced at: 2 months ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 1
tscheipel/HaDes-V
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
Language: SystemVerilog - Size: 432 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 35 - Forks: 2
tymonx/virtio
Virtio implementation in SystemVerilog
Language: SystemVerilog - Size: 44.9 KB - Last synced at: 3 months ago - Pushed at: over 7 years ago - Stars: 47 - Forks: 11
masaki-wk/verilator-example
A simple example of how to use Verilator
Language: SystemVerilog - Size: 8.79 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0
shsjung/sequential-multiply-divide
Language: SystemVerilog - Size: 18.6 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0
RISMicroDevices/RMR8PM3001A
Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC
Language: C++ - Size: 557 KB - Last synced at: about 2 months ago - Pushed at: about 3 years ago - Stars: 9 - Forks: 1
sifferman/fusesoc_project_template
A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
Language: Makefile - Size: 4.88 KB - Last synced at: 7 days ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 0
IBM/hdl-tools 📦
Facilitates building open source tools for working with hardware description languages (HDLs)
Language: Perl - Size: 40 KB - Last synced at: 3 days ago - Pushed at: over 5 years ago - Stars: 63 - Forks: 12
ben-marshall/croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
Language: SystemVerilog - Size: 754 KB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 44 - Forks: 7
ZipCPU/autofpga
A utility for Composing FPGA designs from Peripherals
Language: C++ - Size: 2.42 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 170 - Forks: 19
yasnakateb/ChipyardIntegration
😱 RoCC Accelerator Integration with Chipyard
Size: 8.79 KB - Last synced at: about 2 months ago - Pushed at: 7 months ago - Stars: 3 - Forks: 0
Flinner/PacmanFPGA
Classic Pacman Implementation on a Xilinx FPGA! Simulated with Verilator + SFML
Language: SystemVerilog - Size: 12.1 MB - Last synced at: 2 months ago - Pushed at: 6 months ago - Stars: 2 - Forks: 1
ZipCPU/wbi2c
Wishbone controlled I2C controllers
Language: Verilog - Size: 759 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 44 - Forks: 10
SinaKarvandi/hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
Language: VHDL - Size: 46.9 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 2
ZipCPU/openarty
An Open Source configuration of the Arty platform
Language: Verilog - Size: 14.2 MB - Last synced at: 7 months ago - Pushed at: over 1 year ago - Stars: 122 - Forks: 24
ZipCPU/dpll
A collection of phase locked loop (PLL) related projects
Language: Verilog - Size: 690 KB - Last synced at: 6 months ago - Pushed at: over 1 year ago - Stars: 99 - Forks: 26
RDSik/si5340-config-loader
Module for load configuration from ClockBuilderPro to Si5340 PLL via i2c interface
Language: Verilog - Size: 2.15 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 1
ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
Language: Verilog - Size: 256 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1,289 - Forks: 154
ZipCPU/videozip
A ZipCPU SoC for the Nexys Video board supporting video functionality
Language: Verilog - Size: 9.34 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 16 - Forks: 1
watbulb/tt-toolchain-build
A Linux-Local Installation of TT tools at version parity with TinyTapeout Selected Versions (see branch name)
Language: Shell - Size: 60.5 KB - Last synced at: 8 days ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
ArbnorSh/RV-PipelineCore
RISC-V processor in compliance with RV32IMZicsr
Language: Verilog - Size: 1.82 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 3 - Forks: 0
tum-ei-eda/vrtlmod
vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/Clang-Tools and generates a fault injection API.
Language: C++ - Size: 601 KB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 13 - Forks: 5
DaulPavid/verilog_template
Boilerplate project template for verilog that includes directories for simulation, documentation, and formal verification.
Language: CMake - Size: 43 KB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 0
muhammadtalhasami/RV32I_Single_Cycle
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
Language: Verilog - Size: 168 KB - Last synced at: about 1 month ago - Pushed at: 10 months ago - Stars: 3 - Forks: 0
esynr3z/playhdl
🪀 Tool to play with HDL (inspired by EdaPlayground)
Language: Python - Size: 27.3 KB - Last synced at: 10 months ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 1
microdynamics-cpu/tree-core-cpu
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
Language: Scala - Size: 669 KB - Last synced at: 7 months ago - Pushed at: over 1 year ago - Stars: 36 - Forks: 3
ZipCPU/wbuart32
A simple, basic, formally verified UART controller
Language: Verilog - Size: 1.19 MB - Last synced at: 10 months ago - Pushed at: over 1 year ago - Stars: 266 - Forks: 46
memchk/cbench
A verilator testbench framework.
Language: C++ - Size: 11.7 KB - Last synced at: 3 months ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 0
capopaul/Public-Verilog-Design-Flow-And-Environment
Provide a basic structure to starts a Verilog project. Create a Verilog Design Flow based on Makefiles, Iverilog, GTKwave. Create a VS Code environment with Linting (verilator and verible), formatting and Language Server (verible)
Language: Verilog - Size: 3.91 KB - Last synced at: 11 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
ZipCPU/interpolation
Digital Interpolation Techniques Applied to Digital Signal Processing
Language: Verilog - Size: 2.04 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 48 - Forks: 12
muhammadtalhasami/Axi4_lite_interface
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
Language: SystemVerilog - Size: 104 KB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 1
aakash-n-gupta/ASICBlocks
System Level Simulation and ASIC hardening flow for various designs using Systemverilog, Verilator and OpenROAD
Language: Verilog - Size: 38.1 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
lbnlcomputerarch/vte
Verilator Testbench Environment
Language: C++ - Size: 131 KB - Last synced at: 7 months ago - Pushed at: over 6 years ago - Stars: 3 - Forks: 1
2uger/tiny_soc
Simple implementation of SOC around PicoRV32 soft core.
Language: Verilog - Size: 31.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0
embed-dsp/ed_verilator
Compile and Install of Verilator Tool (Compiles synthesizable Verilog / SystemVerilog into C++ and SystemC code)
Language: Makefile - Size: 21.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
usedhondacivic/fpga_raymarching_gpu
FPGA based GPU for rendering ray marched scenes.
Language: Verilog - Size: 39 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
arhamhashmi01/Axi4-lite
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
Language: SystemVerilog - Size: 390 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
mwbryant/uart-CI
Basic continous integration testing for verilog projects
Language: C++ - Size: 6.84 KB - Last synced at: about 1 year ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0
ZipCPU/dblclockfft
A configurable C++ generator of pipelined Verilog FFT cores
Language: C++ - Size: 1.08 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 204 - Forks: 28
hsnaves/gigatron
Verilog model and simulator (emulator) for the Gigatron TTL microcomputer .
Language: C - Size: 43 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 1
fredrequin/verilator_gowin
Re-coded Gowin GW1N primitives for Verilator use
Language: Verilog - Size: 31.3 KB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 9 - Forks: 0
fredrequin/verilator_xilinx
Re-coded Xilinx primitives for Verilator use
Language: Verilog - Size: 151 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 30 - Forks: 2
CricySaray/verilator-basic-practice
The practice of learning Verilator Basic from itsembedded.com.
Language: C++ - Size: 3.92 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
supleed2/axiTest
AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.
Language: SystemVerilog - Size: 8.79 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
supleed2/apbDriver
Basic APB-compatible module designed for use with Verilator, but should work with any DPI-C compatible simulator.
Language: SystemVerilog - Size: 10.7 KB - Last synced at: 6 months ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
semify-eda/go.debug
Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
Language: SystemVerilog - Size: 11.9 MB - Last synced at: 25 days ago - Pushed at: over 3 years ago - Stars: 10 - Forks: 3
kkiningh/rules_verilator
Bazel build rules for Verilator
Language: Starlark - Size: 37.1 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 20 - Forks: 14
MrAMS/hello_chisel
A Chisel Template with VERILATOR and NVBoard
Language: Scala - Size: 13.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
aitesam961/lynx-VTL
A codebase for learning effective use of verilator
Language: C++ - Size: 218 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
stornado/Open-IC-DEV
Open IC DEV 是一个基于 iVerilog, SystemC, UVM, verible, verilator, oh-my-zsh，vscode 等开源工具链的开发环境。
Language: Dockerfile - Size: 28.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
akashlevy/NEM-Relay-CGRA
Jade CGRA using NEM relay interconnect fabric. Related repositories: NEM-Relay-CGRA-Flow, NEM-Relay-CAD
Language: Verilog - Size: 1.74 GB - Last synced at: 6 days ago - Pushed at: almost 4 years ago - Stars: 8 - Forks: 4
a2k-hanlon/linter-veriloghdl 📦
Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.
Language: CoffeeScript - Size: 784 KB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 9 - Forks: 2
Rafa350/riscv
Experimental RISCV implementation
Language: SystemVerilog - Size: 798 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 0
