GitHub topics: soft-core
wyvernSemi/riscV
Open source ISS and logic RISC-V 32 bit project
Language: C++ - Size: 73.5 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 53 - Forks: 15
stnolting/neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Language: VHDL - Size: 226 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 1,774 - Forks: 263
lxp32/lxp32-cpu
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
Language: Assembly - Size: 3.4 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 60 - Forks: 14
sy2002/QNICE-FPGA
QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.
Language: Assembly - Size: 32 MB - Last synced at: 10 days ago - Pushed at: 8 months ago - Stars: 72 - Forks: 17
saursin/riscv-atom
An open-source 32-bit RISC-V soft-core processor
Language: C++ - Size: 2.9 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 34 - Forks: 15
stnolting/neo430 📦
:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
Language: VHDL - Size: 44.3 MB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 202 - Forks: 28
alinja/alpus_riscv_cpu
A study of soft-core CPUs for use with FPGA designs
Language: Verilog - Size: 136 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 2 - Forks: 0
wyvernSemi/mico32
LatticeMico32 instruction set simulator project
Language: C++ - Size: 12.3 MB - Last synced at: about 2 months ago - Pushed at: 6 months ago - Stars: 9 - Forks: 3
ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
Language: Verilog - Size: 256 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1,289 - Forks: 154
ArbnorSh/RV-PipelineCore
RISC-V processor in compliance with RV32IMZicsr
Language: Verilog - Size: 1.82 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 3 - Forks: 0
WangXuan95/FPGA-DDR-SDRAM
An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
Language: Verilog - Size: 437 KB - Last synced at: 12 months ago - Pushed at: over 1 year ago - Stars: 129 - Forks: 25
BrosnanYuen/MIPS_Processor
16-bit MIPS Processor from scratch in VHDL
Language: VHDL - Size: 358 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
AndrejChoo/AVR_like_core_on_verilog
Soft core with support for the AVR8 instructions on verilog
Language: Verilog - Size: 475 KB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0
mrisc32/mrisc32-a1 📦
A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
Language: VHDL - Size: 512 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 22 - Forks: 5
true-grue/uzh
Uzh compiler
Language: Python - Size: 80.1 KB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 6 - Forks: 0
semahawk/icarium
Trying to implement a soft core SoC
Language: Verilog - Size: 559 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 4 - Forks: 0
FREEWING-JP/zpu Fork of zylin/zpu
The Zylin ZPU
Size: 14.2 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
FREEWING-JP/zpugcc Fork of zylin/zpugcc
How to build Zylin ZPU's GCC toolchain with Windows WSL 2022
Language: C - Size: 141 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
RainingComputers/SRP16
SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.
Language: C++ - Size: 21.9 MB - Last synced at: 2 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
