GitHub topics: risc-cpu
lxp32/lxp32-cpu
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
Language: Assembly - Size: 3.4 MB - Last synced at: 24 days ago - Pushed at: 24 days ago - Stars: 60 - Forks: 14
ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
Language: Verilog - Size: 256 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1,289 - Forks: 154
BrosnanYuen/MIPS_Processor
16-bit MIPS Processor from scratch in VHDL
Language: VHDL - Size: 358 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
Howeng98/RISC-V-CPU
risc-v-cpu
Language: Assembly - Size: 1.43 MB - Last synced at: about 1 year ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0
kianmajl/A2K-CPU
A 32-bit single cycle RISC CPU based on Harvard architecture with no cache or pipeline, by having very simple and reduced instruction set it can be used for educational purpose.
Language: Verilog - Size: 294 KB - Last synced at: 21 days ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
EmbeddedCamerata/Simple-RISC-CPU
Simple RISC CPU. 根据夏宇闻《Verilog数字系统设计教程》第2版17.1节简化RISC_CPU设计修改
Language: Verilog - Size: 31.3 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
FREEWING-JP/zpu Fork of zylin/zpu
The Zylin ZPU
Size: 14.2 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
uttamsaha/14-bit-RISC-CPU-Implementation
14-bit CPU implementation in Logisim. This is a 14-bit RISC CPU logisim implementation. All files are included in this single repository.
Language: C++ - Size: 363 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
