K4V4NH/Basic-Verilog-Codes

Compiled set of verilog codes for beginners. Can help you with getting started with basics of verilog.

Language: Verilog - Size: 18.6 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.28 MB - Last synced at: 1 day ago - Pushed at: 3 days ago - Stars: 323 - Forks: 81

johnnycubides/digital-electronic-1-101

Language: Verilog - Size: 37.6 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 6 - Forks: 2

superphosphate/verilog-with-iverilog-gtkwave

A Visual Studio Code extension for compiling Verilog modules with Iverilog and simulating results with GTKWave.

Language: TypeScript - Size: 68.4 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 0 - Forks: 0

OpenEDF/verilog-basic

learn the combinational and sequential logic circuit.

Language: SystemVerilog - Size: 24.3 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 15 - Forks: 1

Pa1mantri/VSD_Hardware_Design

Pre and Post Synthesis Simulation of a Design VSDMemSOC

Language: Verilog - Size: 6.63 MB - Last synced at: 23 days ago - Pushed at: 23 days ago - Stars: 2 - Forks: 1

yasnakateb/PipelinedMIPS

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

Language: Verilog - Size: 75.2 KB - Last synced at: 5 days ago - Pushed at: almost 5 years ago - Stars: 10 - Forks: 0

JeffDeCola/my-verilog-examples

A place to keep my synthesizable verilog examples.

Language: Verilog - Size: 13.7 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 36 - Forks: 11

TheSUPERCD/8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

Language: Verilog - Size: 173 KB - Last synced at: 3 months ago - Pushed at: over 2 years ago - Stars: 54 - Forks: 15

patrickleboutillier/jcscpu-hw

Hardware implementation, using a Digilent Basys-3 FPGA board, of the computer described in J. Clark Scott's book "But How Do It Know?".

Language: Verilog - Size: 268 KB - Last synced at: 3 months ago - Pushed at: almost 5 years ago - Stars: 15 - Forks: 3

freand76/gowin_fpga_sim_models

Simulation models for GOWIN FPGA primitives

Language: Verilog - Size: 0 Bytes - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

yasnakateb/UARTCommunication

☎️ UART Communication Implementation in Verilog HDL

Language: Verilog - Size: 4.88 KB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 0

mkfahim/Iverilog-GTKWave

Verilog simulations with Icarus Verilog and waveform display via GTKWave

Size: 0 Bytes - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

AbinashDwibedi/learning-verilog

A repository dedicated to learning Verilog, featuring examples, testbenches, simulations, and gate-level designs. Perfect for beginners and enthusiasts exploring hardware description languages.

Language: Verilog - Size: 1.35 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

sgherbst/svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

Language: SystemVerilog - Size: 253 KB - Last synced at: 9 days ago - Pushed at: over 4 years ago - Stars: 44 - Forks: 9

VarshithGovi/Logic_gates

Simulate and analyze fundamental logic gates using Icarus Verilog and GTKWave. This project provides a modular Verilog implementation and a comprehensive testbench for precise validation, offering valuable insights into digital design workflows for VLSI professionals.

Language: Verilog - Size: 33.2 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

eleven-3/fft_verilog

使用verilog实现流水线 FFT

Language: Verilog - Size: 264 KB - Last synced at: 4 days ago - Pushed at: 12 months ago - Stars: 13 - Forks: 1

VarshithGovi/Half-Adder-Design-Verilog

A compact Verilog project implementing a half-adder with gate-level modeling, featuring a detailed testbench for functional verification and simulation.

Language: Verilog - Size: 23.4 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

kambadur/Projects

Everything related to MCUs, FPGAs, C, Verilog, Matlab/Simullink

Language: C - Size: 72.5 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

yasnakateb/NoCRouter

👶🏻 My first baby steps into the world of NoC

Language: Verilog - Size: 269 KB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 11 - Forks: 2

yasnakateb/PipelinedARM

💎 A 32-bit ARM Processor Implementation in Verilog HDL

Language: Verilog - Size: 55.7 KB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 19 - Forks: 3

mshr-h/fibonacci_verilog

fibonacci number calculator written in Verilog-HDL

Language: Verilog - Size: 41 KB - Last synced at: 19 days ago - Pushed at: over 8 years ago - Stars: 4 - Forks: 0

TimRudy/ice-chips-verilog

IceChips is a library of all common discrete logic devices in Verilog

Language: Verilog - Size: 1.42 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 135 - Forks: 23

yasnakateb/SdramController

🛠 A SDRAM controller in Verilog HDL

Language: Verilog - Size: 47.9 KB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

yasnakateb/AES

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

Language: Verilog - Size: 32.2 KB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

sakthispgs/VSDsquadronmini_intern

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

Size: 749 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

capopaul/Public-Verilog-Design-Flow-And-Environment

Provide a basic structure to starts a Verilog project. Create a Verilog Design Flow based on Makefiles, Iverilog, GTKwave. Create a VS Code environment with Linting (verilator and verible), formatting and Language Server (verible)

Language: Verilog - Size: 3.91 KB - Last synced at: 12 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

ErickMaRi/Proyecto-Digitales-II

Diseño de un par controlador-periférico según el protocolo MDIO (cláusula 22)

Language: Verilog - Size: 1.57 MB - Last synced at: 3 months ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0

calint/zen-one

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga cmod s7 from digilent

Language: Verilog - Size: 462 KB - Last synced at: 4 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

pytec8800/pint_iverilog

Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.

Language: C++ - Size: 3.45 MB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 12 - Forks: 3

Katanta/IDATT2104-HDL

Repository exploring Hardware Description Languages through simple demos

Language: Verilog - Size: 636 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

embed-dsp/ed_iverilog

Compile and Install of Icarus Verilog Tool (Verilog Compilation and Simulation System)

Language: Makefile - Size: 19.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

maazm007/vsdsquadron-mini-internship

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

Language: C - Size: 5.79 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 5 - Forks: 0

BhattSoham/RISCV-HDP

Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)

Language: Verilog - Size: 42.7 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

calint/riscv

experiments implementing a risc-v cpu to gain experience with verilog and minimalistic cpu design

Language: Verilog - Size: 920 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Toby-Shi-cloud/verilog-project

Develop for BUAA CO.

Language: TypeScript - Size: 156 KB - Last synced at: 11 days ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 1

dpretet/meduram

Multi-port BRAM IP for ASIC and FPGA

Language: SystemVerilog - Size: 241 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 10 - Forks: 2

arjunrajasekharan/16-bit-DADDA-Multiplier

16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.

Language: Verilog - Size: 27.3 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 0

supleed2/ELEC40006-P1-CW

Yr1 Summer Term Project, ARM-based CPU designed to be simulated in Icarus Verilog

Language: Verilog - Size: 66.7 MB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 2

siri-n-shetty/Car-Parking-System-iverilog

Laboratory Mini Project for the Course - Digital Design and Computer Organization (UE22CS251A)

Language: Verilog - Size: 1.35 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Essenceia/ethernet-physical-layer

RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

Language: Tcl - Size: 385 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 3

stornado/Open-IC-DEV

Open IC DEV 是一个基于 iVerilog, SystemC, UVM, verible, verilator, oh-my-zsh，vscode 等开源工具链的开发环境。

Language: Dockerfile - Size: 28.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

a2k-hanlon/linter-veriloghdl 📦

Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.

Language: CoffeeScript - Size: 784 KB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 9 - Forks: 2

Tech-mohankrishna/pes_bcdbin

This repository deals with BCD to binary conversion using iverilog as a simulator and yosys as a synthesis tool.

Language: Verilog - Size: 64.5 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

ArvinDelavari/Digital-Circuits-Verilog

Sample Verilog codes for digital circuits

Language: HTML - Size: 9.31 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

MananAgarwal/Computer-Architecture

Lab exercises of the course F342 Computer Architecture

Language: Verilog - Size: 8.79 KB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

D3r3k23/iVerilogTemplate

Icarus Verilog, GTKWave

Language: Verilog - Size: 5.86 KB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

GokuGhoul/Embd-iverilog

Embedded Systems Lab Work

Language: Verilog - Size: 24.4 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

rohanverma94/200DaysWithFPGAs

The objective of this project is to explore ray tracing and design a soft GPU on Xilinx Artix 100T.

Size: 3.91 KB - Last synced at: 2 days ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

ParimalaS27/Parallel-Prefix-Adder-8bit-UE19CS206-DDCOLab

This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.

Language: Verilog - Size: 497 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 2

jfcherng-sublime/SublimeLinter-contrib-iverilog

This linter plugin for SublimeLinter provides an interface to iverilog (verilog compiler).

Language: Python - Size: 531 KB - Last synced at: 2 days ago - Pushed at: about 1 year ago - Stars: 13 - Forks: 1

TimRudy/uart-verilog

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

Language: Verilog - Size: 26.7 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

arjunrajasekharan/16bit-Sklansky-Adder

16-bit Slansky Adder design using verilog HDL

Language: Verilog - Size: 361 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 1

suraj-2306/ProcessorDesign

Implementation of 4 stage pipelined 8 bit RISC-V processor

Language: Verilog - Size: 7.81 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

strongwong/bittyCore_RISC-V

This is a bitty CPU core of risc-v architecture, which is currently under development.

Language: Verilog - Size: 1.3 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 8 - Forks: 3

mishal23/coa

Assignments pertaining to Course CO200 - Computer Organization and Architecture

Language: Verilog - Size: 4.16 MB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 1

smsraj2001/RING-AND-JOHNSONS-COUNTER

An iverilog program displaying the working of RING and JOHNSONS counter with the Timing diagram in GTK wave.

Language: Verilog - Size: 8.79 KB - Last synced at: 4 months ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

EmbeddedCamerata/Simple-RISC-CPU

Simple RISC CPU. 根据夏宇闻《Verilog数字系统设计教程》第2版17.1节简化RISC_CPU设计修改

Language: Verilog - Size: 31.3 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

ashishrana160796/verilog-starter-tutorials 📦

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

Language: Verilog - Size: 25.4 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 34 - Forks: 17

ruibailin/FtoCDT

C/C++ projects which are friendly to Eclipse CDT

Size: 82.7 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

Adarsh275/Project-Booths-Multiplier

Language: Verilog - Size: 656 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

Adarsh275/DDCO-LAB-16-Bit-Microprocessor

Language: Verilog - Size: 12.2 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

rodrigomelo9/verifying-foss-hdl-synthesizers

a project to check the FOSS synthesizers against vendors EDA tools

Language: Makefile - Size: 81.1 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 12 - Forks: 2

LastRagnarokkr/mips16-iverilog

A processor implementation in Icarus Verilog (iVerilog), 16bit MIPS format.

Language: Verilog - Size: 25.4 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

puneeth714/parity_calc

parity calculator for the given bit stream

Language: Python - Size: 242 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

yoyozaemon/DDCO-Lab-UE20CS256

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE20CS256) at PES University.

Language: Verilog - Size: 57.6 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

kambadur/sky130RTLDesignAndSynthesisWorkshop

This is a 5-day workshop on RTL Design and Synthesis using open source tools for logic design, simulation, synthesis and technology mapping with Sky130 PDK. (iVerilog, GTKwave, Yosys and Sky130 technology)

Size: 4.33 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 1

okoge-kaz/Computer_Logic_Design

2022-1Q コンピュータ論理設計 (Tokyo Tech)

Language: Verilog - Size: 7.25 MB - Last synced at: 3 months ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

paranlee/guarded_unsigned_counter

Counter with two guardians who count each bit either even or odd.

Language: Verilog - Size: 19.5 KB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

zhouxs1023/setup_script

setup script for iverilog+gtkwave by inno setup

Language: Inno Setup - Size: 2.93 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

JacobLondon/SoftProcessorWatermark

A MIPS softcore processor to average images together and output to VGA on a Nexys 4 DDR FPGA.

Language: C++ - Size: 108 MB - Last synced at: about 2 years ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 2

pangguoming/iview-admin Fork of iview/iview-admin

Vue 2.0 admin management system template based on iView 个人修改版

Language: JavaScript - Size: 46.4 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 13 - Forks: 14

sanjaytharagesh31/Computer-Organization-and-Architecture

Verilog codes developed as a part of COA lab course

Language: Verilog - Size: 96.7 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 1

grantslape/txstate-iverilog

A repo for CS 3339 students learning verilog

Language: Verilog - Size: 11.6 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0