Ecosyste.ms: Repos

An open API service providing repository metadata for many open source software ecosystems.

GitHub topics: uvm

Repositories

rggen/rggen-sample-testbench

Language: VHDL - Size: 242 KB - Last synced: about 24 hours ago - Pushed: 1 day ago - Stars: 15 - Forks: 3

cocotb/cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Language: Python - Size: 7.48 MB - Last synced: about 21 hours ago - Pushed: 1 day ago - Stars: 1,636 - Forks: 482

PacoReinaCampo/UVM

Standard Universal Verification Methodology

Language: SystemVerilog - Size: 20.6 MB - Last synced: 1 day ago - Pushed: 1 day ago - Stars: 8 - Forks: 4

PacoReinaCampo/SoC-DV

System on Chip verified with UVM/OSVVM/FV

Language: SystemVerilog - Size: 22.8 MB - Last synced: 1 day ago - Pushed: 1 day ago - Stars: 20 - Forks: 6

PacoReinaCampo/PU-DV

Processing Unit verified with UVM/OSVVM/FV

Language: SystemVerilog - Size: 13.6 MB - Last synced: 1 day ago - Pushed: 1 day ago - Stars: 4 - Forks: 4

KLYN74R/Web1337

A gateway for amazing Web1337 by KLYNTAR

Language: JavaScript - Size: 3.58 MB - Last synced: 1 day ago - Pushed: 1 day ago - Stars: 3 - Forks: 0

Dragon-Git/icdk

uvm framework generator

Language: SystemVerilog - Size: 109 KB - Last synced: 1 day ago - Pushed: 1 day ago - Stars: 4 - Forks: 1

Gonadeepika/virtual-interface

in this repository is there in how to write virtual interface

Language: SystemVerilog - Size: 19.5 KB - Last synced: 5 days ago - Pushed: 5 days ago - Stars: 0 - Forks: 0

Gonadeepika/phases

in this repository is there in how to write phases

Language: SystemVerilog - Size: 0 Bytes - Last synced: 5 days ago - Pushed: 5 days ago - Stars: 0 - Forks: 0

Gonadeepika/factory-overridibg

in this repository is there in factory overiding

Language: SystemVerilog - Size: 0 Bytes - Last synced: 5 days ago - Pushed: 5 days ago - Stars: 0 - Forks: 0

DigitalLabIIESTS/VLSI-Front-End

Requirements for VLSI front-end Engineer

Size: 3.1 MB - Last synced: 7 days ago - Pushed: 8 days ago - Stars: 3 - Forks: 1

chipsalliance/Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Language: C++ - Size: 831 MB - Last synced: 7 days ago - Pushed: 8 days ago - Stars: 331 - Forks: 66

Nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Language: Python - Size: 19 MB - Last synced: 7 days ago - Pushed: 8 days ago - Stars: 193 - Forks: 26

taichi-ishitani/tvip-axi

AMBA AXI VIP

Language: SystemVerilog - Size: 147 KB - Last synced: 9 days ago - Pushed: 9 days ago - Stars: 300 - Forks: 94

esynr3z/eda-log-colorizer

🎨 Colorize your boring EDA logs

Language: Shell - Size: 372 KB - Last synced: 9 days ago - Pushed: 9 days ago - Stars: 2 - Forks: 2

troyguo/awesome-dv

Awesome ASIC design verification

Size: 18.6 KB - Last synced: 3 days ago - Pushed: over 2 years ago - Stars: 221 - Forks: 58

SystemRDL/PeakRDL

Control and status register code generator toolchain

Language: Python - Size: 125 KB - Last synced: 4 days ago - Pushed: 7 months ago - Stars: 74 - Forks: 16

SystemRDL/PeakRDL-uvm

Generate UVM register model from compiled SystemRDL input

Language: Python - Size: 63.5 KB - Last synced: 13 days ago - Pushed: 4 months ago - Stars: 45 - Forks: 24

KeerthanaPrabhu04/UVM_TestBench_For_4-to-2_Encoder

Language: SystemVerilog - Size: 18.6 KB - Last synced: 14 days ago - Pushed: 14 days ago - Stars: 0 - Forks: 0

dvtalk/dvtalk.github.io Fork of just-the-docs/just-the-docs

Language: SCSS - Size: 5.96 MB - Last synced: 15 days ago - Pushed: 15 days ago - Stars: 4 - Forks: 1

yuravg/uvm_tb_cross_bar

SystemVerilog UVM testbench example

Language: SystemVerilog - Size: 223 KB - Last synced: 15 days ago - Pushed: 15 days ago - Stars: 20 - Forks: 10

rggen/rggen-systemverilog

SystemVerilog RTL and UVM RAL model generators for RgGen

Language: Ruby - Size: 608 KB - Last synced: 17 days ago - Pushed: 4 months ago - Stars: 11 - Forks: 1

postmanlabs/uvm

Universal Virtual Machine for Node and Browser

Language: JavaScript - Size: 2.08 MB - Last synced: 2 days ago - Pushed: 16 days ago - Stars: 36 - Forks: 24

taichi-ishitani/tnoc

Network on Chip Implementation written in SytemVerilog

Language: SystemVerilog - Size: 406 KB - Last synced: 21 days ago - Pushed: over 1 year ago - Stars: 133 - Forks: 40

maximecb/uvm

Fun, portable, minimalistic virtual machine.

Language: Rust - Size: 1.44 MB - Last synced: 21 days ago - Pushed: 25 days ago - Stars: 503 - Forks: 19

Juniper/open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Language: Verilog - Size: 7.03 MB - Last synced: 1 day ago - Pushed: 10 months ago - Stars: 182 - Forks: 66

erihsu/INT_FP_MAC

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

Language: Verilog - Size: 20 MB - Last synced: 28 days ago - Pushed: over 3 years ago - Stars: 60 - Forks: 11

openhwgroup/core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Language: Assembly - Size: 109 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 377 - Forks: 196

contactpro/UVM_Command_Center

UVM Command Center - UVM Testbench Builder (DEMO) - Demo of UVM Verification Workflow IDE.

Language: Python - Size: 5.32 MB - Last synced: about 2 months ago - Pushed: 2 months ago - Stars: 4 - Forks: 3

taichi-ishitani/tue

Useful UVM extensions

Language: SystemVerilog - Size: 96.7 KB - Last synced: 21 days ago - Pushed: about 2 months ago - Stars: 19 - Forks: 4

PacoReinaCampo/MPSoC-DV

Multi-Processor System on Chip verified with UVM/OSVVM/FV

Language: SystemVerilog - Size: 34.8 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 25 - Forks: 14

williaml33moore/bathtub Fork of everactive/bathtub

BDD Gherkin implementation in native SystemVerilog, based on UVM.

Language: SystemVerilog - Size: 7.04 MB - Last synced: 25 days ago - Pushed: 25 days ago - Stars: 2 - Forks: 0

Ghonimo/Formal-Verification-of-an-AHB2APB-Bridge

Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation including a final report and project progression presentation.

Language: SystemVerilog - Size: 14.2 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 1 - Forks: 0

Shehab-Naga/ddr5_phy

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

Language: SystemVerilog - Size: 13 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 34 - Forks: 16

amamory-ursa/hf-risc Fork of sjohann81/hf-risc

HF-RISC SoC

Language: C - Size: 7.92 MB - Last synced: 2 months ago - Pushed: almost 5 years ago - Stars: 1 - Forks: 5

taichi-ishitani/tvip-apb

Verification IP for AMBA APB Protocol

Language: SystemVerilog - Size: 24.4 KB - Last synced: 21 days ago - Pushed: 7 months ago - Stars: 19 - Forks: 6

tymonx/logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Language: SystemVerilog - Size: 820 KB - Last synced: 2 months ago - Pushed: over 4 years ago - Stars: 248 - Forks: 53

Dragon-Git/uvm_syoscb

Language: SystemVerilog - Size: 10.4 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 1 - Forks: 0

taichi-ishitani/rggen 📦

This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).

Language: Ruby - Size: 1.53 MB - Last synced: 21 days ago - Pushed: almost 5 years ago - Stars: 16 - Forks: 3

SerLippo/Lemmings

This is a simple UVM env for DV starters.

Language: SystemVerilog - Size: 15.6 KB - Last synced: 3 months ago - Pushed: about 2 years ago - Stars: 2 - Forks: 0

angeliaplutus/ipcoredesign

Design & Verification of IP Cores and ICs, Artificial Intelligence

Language: VHDL - Size: 18.4 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 1 - Forks: 1

JoseIuri/Simple_UVM

Implements a simple UVM based testbench for a simple memory DUT.

Language: SystemVerilog - Size: 56.6 KB - Last synced: 3 months ago - Pushed: over 4 years ago - Stars: 10 - Forks: 5

JoseIuri/Aurora

Automatic testbench and reference flow generation tool compatible with UVM and SVA.

Language: Python - Size: 23.8 MB - Last synced: 3 months ago - Pushed: over 3 years ago - Stars: 6 - Forks: 0

JoseIuri/Aproximated-UVM

This repository contains a proposal UVM testbench for aproximated circuits.

Language: SystemVerilog - Size: 7.04 MB - Last synced: 3 months ago - Pushed: over 4 years ago - Stars: 0 - Forks: 4

Ghonimo/Pre_Silicon-AHB-to_APB-Verification

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

Language: SystemVerilog - Size: 13.5 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 5 - Forks: 2

Artityagi123456789/15DaysofUVM

Language: SystemVerilog - Size: 24.2 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 6 - Forks: 1

sdnellen/open-register-design-tool Fork of Juniper/open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Language: Verilog - Size: 7.03 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 15 - Forks: 3

andreemedeiros/Huffman-UVM

Projeto de verificação UVM para um RTL de Decodificador de Huffman.

Language: SystemVerilog - Size: 81.1 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 2 - Forks: 0

rggen/rggen

Code generation tool for configuration and status registers

Language: Ruby - Size: 497 KB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 257 - Forks: 36

loideyron/uvm_gen Fork of hjking/uvm_gen

Vim UVM Generator Plugin

Language: Vim Script - Size: 60.5 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

taichi-ishitani/rice

Language: SystemVerilog - Size: 273 KB - Last synced: 21 days ago - Pushed: 8 months ago - Stars: 3 - Forks: 2

semify-eda/go.debug

Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

Language: SystemVerilog - Size: 11.9 MB - Last synced: 25 days ago - Pushed: over 2 years ago - Stars: 10 - Forks: 2

ayengec/FPGA-Design-with-Systemverilog

SystemVerilog brings a higher level of abstraction to the Verilog designer. Constructs and commands like Interfaces, new Data types (logic, int), Enumerated types, Arrays, Hardware-specific always (always_ff, always_comb) and others allow modeling of RTL designs easily, and with less coding.

Language: SystemVerilog - Size: 39.5 MB - Last synced: 5 months ago - Pushed: about 2 years ago - Stars: 1 - Forks: 2

kaushalmodi/custom_uvm_report_server

Customized UVM Report Server

Language: SystemVerilog - Size: 424 KB - Last synced: 2 months ago - Pushed: over 4 years ago - Stars: 31 - Forks: 7

ChungKee/UVM-Testbench-Generator

Generate the uvm testbench automatically

Language: Python - Size: 158 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 1 - Forks: 0

wooga/unity-version-manager-jni

JNI bindings for the unity version manager

Language: Groovy - Size: 379 KB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 3

stornado/Open-IC-DEV

Open IC DEV 是一个基于 iVerilog, SystemC, UVM, verible, verilator, oh-my-zsh，vscode 等开源工具链的开发环境。

Language: Dockerfile - Size: 28.3 KB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

minecraftdixit/Digital-ASIC-LAB

Verilog Codes for various Design for lab at IIT Jodhpur

Language: SystemVerilog - Size: 755 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

rggen/rggen-sv-ral

UVM RAL class package for RgGen

Language: SystemVerilog - Size: 47.9 KB - Last synced: 21 days ago - Pushed: 4 months ago - Stars: 5 - Forks: 1

sikderAmit/piso-uvm-verification

This repository contain all the necessary files to verify PISO Universal Register

Language: SystemVerilog - Size: 198 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

SleekPanther/noah-patullo-repositories

A list of projects I've worked on. GitHub's organization is lacking in my opinion, so this serves as an index & root of all my work (I'm Noah Patullo, not Pattullo or Patulo. I have a unique name & this should help clarify who I am)

Size: 29.3 KB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 2 - Forks: 1

amiq-consulting/yamm

YAMM package repository

Language: SystemVerilog - Size: 2.06 MB - Last synced: 7 months ago - Pushed: about 1 year ago - Stars: 21 - Forks: 15

Risto97/systemc_uvm_verilator 📦

Language: C++ - Size: 1.42 MB - Last synced: 7 months ago - Pushed: almost 2 years ago - Stars: 11 - Forks: 0

zhajio1988/YASA

:snail:Yet Another Simulation Architecture

Language: Python - Size: 227 KB - Last synced: 7 months ago - Pushed: over 3 years ago - Stars: 63 - Forks: 33

gupta409/Processor-UVM-Verification

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

Language: Verilog - Size: 354 KB - Last synced: 7 months ago - Pushed: over 6 years ago - Stars: 80 - Forks: 24

21Bruce/UVMTd

System Daemons for testing UVM on OpenBSD

Language: C - Size: 34.2 KB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 1 - Forks: 0

dadongshangu/async_FIFO

This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

Language: SystemVerilog - Size: 178 KB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 40 - Forks: 14

npatsiatzis/recirculation_mux

Language: Python - Size: 10.6 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/fifo_asynchronous

Language: Python - Size: 7.09 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/fizzbuzz

Language: Python - Size: 10.8 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/uart

Language: VHDL - Size: 12.7 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/fifo_synchronous

Language: C++ - Size: 77.1 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

rooinasuit/AXI_to_SPI

Designing means to communicate as an SPI master, being a part of AXI interface

Language: Verilog - Size: 12.7 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 7 - Forks: 2

npatsiatzis/simple_adder

Language: Python - Size: 17.7 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/barrel_shifter

Language: C++ - Size: 7.39 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

hjking/uvm_gen

UVM Generator

Language: SystemVerilog - Size: 45.9 KB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 35 - Forks: 20

npatsiatzis/cdc_handshake

Language: Python - Size: 7.14 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

xiaoweish/uvm-source

Mirror of https://www.accellera.org/downloads/standards/uvm, starting from uvm-1.2.

Language: SystemVerilog - Size: 2.66 MB - Last synced: 28 days ago - Pushed: 9 months ago - Stars: 0 - Forks: 0

john-odonnell/uvm

Based on the 2006 ICFP Programming Contest

Language: C - Size: 141 KB - Last synced: 9 months ago - Pushed: almost 4 years ago - Stars: 0 - Forks: 0

Gonadeepika/100--days--coding--challege

this repo contains codes of rtl for implementation of varipus circuit design using verilog in xilinx ISE 8.1 and sometimes modelsim anf for simulation pupose degital compiler.

Language: SystemVerilog - Size: 36.1 KB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 0 - Forks: 0

AleksandarLilic/AES-256_UVM

UVM testbench for AES-256 VHDL design

Language: SystemVerilog - Size: 783 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

ManjunathKalmath/Digital_Logic_Verification_Using-UVM

Contains simple projects on UVM

Size: 0 Bytes - Last synced: 10 months ago - Pushed: over 3 years ago - Stars: 0 - Forks: 0

AhsanAliUet/Ahsan-Ali-Interests

My interests and some collaborations

Size: 2.93 KB - Last synced: 10 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

chanum/uvm_verification

Examples with UVM

Language: SystemVerilog - Size: 1.2 MB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 2 - Forks: 2

tallendev/uvm-eval

This serves as a repository for reproducibility of the SC21 paper "In-Depth Analyses of Unified Virtual Memory System for GPU Accelerated Computing," as well as several components of the IPDPS21 paper "Demystifying GPU UVM Cost with Deep Runtime and Workload Analysis."

Language: C - Size: 160 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 11 - Forks: 3