GitHub topics: assertion-based-verification
MohamedHussein27/SPI-Slave-with-RAM-UVM
This project uses UVM to verify an SPI Slave connected to internal RAM. It includes multiple agents (active and passive) and integrates assertion-based verification for both SPI and RAM behavior.
Language: SystemVerilog - Size: 8.31 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 0
Ghonimo/Formal-Verification-of-an-AHB2APB-Bridge
Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation including a final report and project progression presentation.
Language: SystemVerilog - Size: 14.2 MB - Last synced at: 3 months ago - Pushed at: about 1 year ago - Stars: 10 - Forks: 4
