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GitHub topics: ahb

Hochfrequenz/edi_energy_scraper

Python script to download/mirror edi-energy.de and sort the files (more structured than `wget --mirror`)

Language: Python - Size: 2.82 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1 - Forks: 1

Hochfrequenz/ahlbatross

highlight changes between AHB documents of consecutive formatversions

Language: Python - Size: 117 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1 - Forks: 0

Hochfrequenz/TransformerBeeClient.NET

A C#/.NET client to communicate with the edifact-bo4e-converter aka transformer.bee

Language: C# - Size: 155 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 1 - Forks: 0

Hochfrequenz/edi_energy_mirror

mirror of edi-energy.de that is periodically updated and allows to track changes

Language: Python - Size: 2.69 GB - Last synced at: 15 days ago - Pushed at: 18 days ago - Stars: 5 - Forks: 1

aignacio/cocotbext-ahb

Cocotb AHB Extension - AHB VIP

Language: Python - Size: 1.37 MB - Last synced at: 29 days ago - Pushed at: 3 months ago - Stars: 14 - Forks: 9

Ghonimo/Formal-Verification-of-an-AHB2APB-Bridge

Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation including a final report and project progression presentation.

Language: SystemVerilog - Size: 14.2 MB - Last synced at: about 2 months ago - Pushed at: about 1 year ago - Stars: 10 - Forks: 4

Hochfrequenz/kohlrahbi

An Anwendungshandbücher (AHB) scraper that extracts tables from docx files

Language: Python - Size: 42.8 MB - Last synced at: 14 days ago - Pushed at: 16 days ago - Stars: 5 - Forks: 2

JN513/verilog-buses-implementations

Popular bus implementations in Verilog HDL

Language: Verilog - Size: 9.77 KB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

Hochfrequenz/mig_ahb_utility_stack 📦

MIG AHB Utility Stack (MAUS): A Script to Match the Message Implementation Guide (MIG) with the Anwendungshandbuch (AHB)

Language: Python - Size: 1.12 MB - Last synced at: 19 days ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

Hochfrequenz/edi_energy_ahb_conditions_and_packages

Condition and Package Definitions extracted from Anwendungshandbüchern (AHB) by EDI@Energy

Size: 653 KB - Last synced at: 28 days ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

ubyhzargam/AMBA-Protocol-Family

This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm

Language: Verilog - Size: 4.88 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

Hochfrequenz/digital_market_communication

Overview of all Hochfrequenz libraries and tools related to an improved digital market communication for German utilities

Size: 61.5 KB - Last synced at: 8 days ago - Pushed at: 5 months ago - Stars: 6 - Forks: 0

rodrigomelo9/amba

A presentation about Advanced Microcontroller Bus Architecture

Language: SystemVerilog - Size: 3.51 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

BoChen-Ye/Tiny_SoC

This is my hobby project, which contain my rsic-v core and my convolutional layer with AMBA bus

Language: Verilog - Size: 179 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

Hochfrequenz/ahbesser-legacy 📦

A Svelte App that displays FlatAnwendungshandbuchs which are generated by kohlrahbi. It displays AHBs _besser_ than edi-energy.de

Language: Svelte - Size: 1.24 MB - Last synced at: 5 days ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0

krevanth/FreeAHB

https://github.com/krevanth/FreeAHB : The official GIT repo of FreeAHB, a FOSS AHB 2.0 manager. (C) 2016-2024 Revanth Kamaraj (krevanth). Note that https://github.com/krevanth/FreeAHB was accidentally deleted but has now been fully restored to the same URL from backups on 22/05/2024. Fork list, issues, stars, watchers couldn't be restored.

Language: SystemVerilog - Size: 1.29 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

DOUDIU/RSA2048

Language: Verilog - Size: 85.3 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 6 - Forks: 1

vicharak-in/vaaman-ahb-verilog

Verilog AHB Bus implementation for VAAMAN

Language: Verilog - Size: 25.4 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

mjh-design/simple-ahb-sram Fork of putongputong-lin/ahb2sram

sram自己写的不是mc生成的

Language: SystemVerilog - Size: 6.84 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

mjh-design/ahb_sram Fork of robinyangyanfeng/ahb_sram

小夫同款

Language: Verilog - Size: 1.41 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

mjh-design/Sram-controller-design-based-on-AHB-bus Fork of wbbbbbb123/Sram-controller-design-based-on-AHB-bus

Language: Verilog - Size: 40 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

lucky-wfw/ARM_AMBA_Design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

Language: Verilog - Size: 2.93 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 61 - Forks: 26

RoaLogic/roalogic.github.io

Roa Logic GitHub Pages Site (Top Level)

Language: SCSS - Size: 196 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 3