GitHub topics: ahb3-lite
PacoReinaCampo/MPSoC-UART
Universal Asynchronous Receiver-Transmitter for MPSoC
Language: SystemVerilog - Size: 21.4 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 3 - Forks: 3

PacoReinaCampo/MPSoC-SPRAM
Single-Port RAM for Instruction & Data for MPSoC
Language: SystemVerilog - Size: 18.5 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 3 - Forks: 2

PacoReinaCampo/MPSoC-MSI
Master Slave Interface for MPSoC
Language: SystemVerilog - Size: 22 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 2 - Forks: 2

PacoReinaCampo/MPSoC-MPRAM
Multi-Port RAM for Instruction & Data for MPSoC
Language: SystemVerilog - Size: 20.6 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 3 - Forks: 4

PacoReinaCampo/MPSoC-MPI
Message Passing Interface for MPSoC
Language: SystemVerilog - Size: 20.3 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 3 - Forks: 1

PacoReinaCampo/MPSoC-GPIO
General Purpose Input Output for MPSoC
Language: SystemVerilog - Size: 20.6 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 3 - Forks: 4

PacoReinaCampo/MPSoC-DMA
Direct Access Memory for MPSoC
Language: SystemVerilog - Size: 21.7 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 12 - Forks: 6

PacoReinaCampo/MPSoC-DBG
Debugger on Chip for MPSoC
Language: SystemVerilog - Size: 28.2 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 2 - Forks: 5

dominiksalvet/super-riscv
Superscalar dual-issue RISC-V processor
Language: SystemVerilog - Size: 1.78 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 7 - Forks: 3

RoaLogic/ahb3lite_interconnect
AHB3-Lite Interconnect
Language: SystemVerilog - Size: 4.84 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 75 - Forks: 26

RoaLogic/ahb3lite_memory
Multi-Technology RAM with AHB3Lite interface
Language: SystemVerilog - Size: 1.5 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 18 - Forks: 16

RoaLogic/ahb3lite_apb_bridge
Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
Language: SystemVerilog - Size: 1.13 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 38 - Forks: 19

RoaLogic/ahb3lite_timer
RISC-V compliant Timer IP
Language: SystemVerilog - Size: 1.73 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 11 - Forks: 7

verilog-indeed/nano4k_ahb_led
Example AHB-lite LED peripheral for the Nano 4K board with embedded Cortex M3 core
Language: GLSL - Size: 752 KB - Last synced at: 10 months ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 2

vicharak-in/vaaman-ahb-verilog
Verilog AHB Bus implementation for VAAMAN
Language: Verilog - Size: 25.4 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

namu00/AMBA_AHB_lite
AMBA AHB-lite studyroom
Language: Verilog - Size: 330 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0
