GitHub topics: instruction-level-parallelism
SIMDE-ULL/SIMDE
Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals
Language: TypeScript - Size: 11.3 MB - Last synced at: 9 days ago - Pushed at: 10 days ago - Stars: 13 - Forks: 10

dominiksalvet/super-riscv
Superscalar dual-issue RISC-V processor
Language: SystemVerilog - Size: 1.78 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 7 - Forks: 3

gocho1307/Labs-OC
Project for 2023/2024 - Computer Organization @ IST
Language: C - Size: 7.61 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

sdasgup3/parallel-processor-design
Super scalar Processor design
Language: Verilog - Size: 137 KB - Last synced at: 2 months ago - Pushed at: almost 11 years ago - Stars: 21 - Forks: 3

alighanbari2002/Parallel-Programming-Course-Projects
Parallel Programming course projects demonstrating various parallelism techniques with SIMD SSE3, OMP, and POSIX threads, including Intel Parallel Studio for analysis and parallelization.
Language: C++ - Size: 7.32 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

CSpyridakis/Tomasulo 📦
Introduction in Dynamic Instruction Scheduling (Advanced Computer Architecture) implementing Tomasulo's Algorithm
Language: VHDL - Size: 8.29 MB - Last synced at: 4 days ago - Pushed at: about 6 years ago - Stars: 4 - Forks: 1

w-feng/CompArch-MIPS-POWER
Curriculum material for teaching computer architecture with MIPS and POWER
Language: Python - Size: 76 MB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 2

scicomp-durham/comp3577-mimd-code
Examples of OpenMP for instruction-level parallelism.
Language: C - Size: 9.77 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

sebastian-wardzinski/computer-architecture
ECE552: Computer Architecture — Fall 2020.
Language: C - Size: 9.66 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 1

sid-xyz/RNBIP_Pipelined-Microprocessor
Redesigned the RNBIP single-bus architecture to implement a 3 stage instruction-level pipeline.
Language: Verilog - Size: 231 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
