GitHub topics: risc

Repositories

BlueGummi/belle

BELLE (Big Endian, Low Level Emulator) The monorepo for a custom 16 bit RISC architecture.

Language: Rust - Size: 5.24 MB - Last synced at: about 3 hours ago - Pushed at: about 4 hours ago - Stars: 6 - Forks: 1

mortbopet/Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

Language: C++ - Size: 43.8 MB - Last synced at: about 12 hours ago - Pushed at: about 13 hours ago - Stars: 2,861 - Forks: 294

Wren6991/RISCBoy

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

Language: C - Size: 49 MB - Last synced at: about 5 hours ago - Pushed at: almost 2 years ago - Stars: 278 - Forks: 14

jcapellman/rvepp-web-contentapp

Content Web App for RVEPP

Language: C# - Size: 109 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

LekKit/RVVM

The RISC-V Virtual Machine

Language: C - Size: 3.72 MB - Last synced at: 3 days ago - Pushed at: 8 days ago - Stars: 1,045 - Forks: 78

mags0ft/JoltCore-16

16-bit RISC CPU with custom ISA, 128 KiB of RAM & ROM, 8 I/O ports, self-written assembler and emulator

Language: Python - Size: 1.74 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

edson-acordi/4bit-microcomputer

MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for educational purposes and distributed for free under open-source licenses.

Language: Python - Size: 16.3 MB - Last synced at: 6 days ago - Pushed at: 7 days ago - Stars: 64 - Forks: 4

five-embeddev/baremetal-cxx-coro

C++20 Coroutines run in baremetal RISC-V, with option to run on native host.

Language: C++ - Size: 4.23 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 6 - Forks: 0

SIMDE-ULL/SIMDE

Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals

Language: TypeScript - Size: 11.3 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 13 - Forks: 10

Choaib-ELMADI/risc-v-on-de1-soc-fpga

A simplified RISC-V processor implemented in Verilog and deployed on the DE-1 SoC FPGA board.

Language: Verilog - Size: 24.3 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 5 - Forks: 2

Kaweees/kiwiRTOS

⏰ A minimal Real-Time Operating System (RTOS) designed for embedded applications with targets for x86_84, RISC-V (RV32I, RV64I) and ARM written in Zig. (🚧 in construction 🚧)

Language: Zig - Size: 5.94 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 1

AluVM/aluvm

AluVM: RISC functional machine base implementation

Language: Rust - Size: 1.42 MB - Last synced at: 2 days ago - Pushed at: 12 days ago - Stars: 61 - Forks: 23

TalesNogueira/Unicycle-MIPS-Based-Computer-System

A Unicycle MIPS-based computer system implementing a RISC architecture, designed to execute instructions generated by a C- Compiler.

Language: Verilog - Size: 19.3 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 0

nikolaydubina/go-hackers-delight

"Hacker's Delight" in Go

Language: Go - Size: 236 KB - Last synced at: 6 days ago - Pushed at: 3 months ago - Stars: 101 - Forks: 4

redthing1/irre-tools

toy handwritten assembler, emulator, compiler, toolchain for a lightweight RISC architecture

Language: D - Size: 1.92 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 2 - Forks: 0

RascalFoxfire/Picowizard

A tiny 8 bit RISC ISA for on-chip/on-FPGA management purposes

Language: SystemVerilog - Size: 50.8 KB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 2 - Forks: 0

openid/sharedsignals

OpenID Shared Signals Working Group Repository

Language: Makefile - Size: 943 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 62 - Forks: 17

chipsalliance/Cores-VeeR-EH1

VeeR EH1 core

Language: SystemVerilog - Size: 17.6 MB - Last synced at: 21 days ago - Pushed at: almost 2 years ago - Stars: 870 - Forks: 227

Diogo-Valadares/Didactic-RISC-I

A rebuild of RISC I architecture, focused in didactic and built in Logisim Evolution

Language: Assembly - Size: 14.8 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

BigEd/XSOC-xr16

System-on-a-Chip for FPGA, with xr16 RISC core and LCC port

Language: C - Size: 3.05 MB - Last synced at: 30 days ago - Pushed at: almost 8 years ago - Stars: 12 - Forks: 0

cjRem44x/CPE310_TRAFFIC_LIGHT

AVR Assembly implementation of a traffic light controller for ATmega328P microcontroller. Educational project demonstrating embedded systems programming fundamentals with timing control and state machine logic.

Language: Assembly - Size: 49.8 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

rrx1c/lunettes-mips-rs

Mips disassembler

Language: Rust - Size: 651 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

MIPT-ILab/mipt-mips 📦

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

Language: C++ - Size: 113 MB - Last synced at: 22 days ago - Pushed at: almost 3 years ago - Stars: 353 - Forks: 138

kvakil/venus

RISC-V instruction set simulator built for education

Language: Kotlin - Size: 1.3 MB - Last synced at: about 1 month ago - Pushed at: about 3 years ago - Stars: 198 - Forks: 60

GMH-Code/RPCEmu

WebAssembly Multi-Threaded Risc PC Emulator

Language: C - Size: 687 KB - Last synced at: about 1 month ago - Pushed at: almost 2 years ago - Stars: 19 - Forks: 0

michaeljclark/rv8

RISC-V simulator for x86-64

Language: C++ - Size: 6.03 MB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 702 - Forks: 101

andrescv/jupiter

RISC-V Assembler and Runtime Simulator

Language: JavaScript - Size: 49.8 MB - Last synced at: about 1 month ago - Pushed at: 11 months ago - Stars: 428 - Forks: 37

vmmc2/Vulcan 📦

RISC-V Instruction Set Simulator (Built for education).

Language: Dart - Size: 3 MB - Last synced at: 17 days ago - Pushed at: over 3 years ago - Stars: 102 - Forks: 10

VB-123/MINI-RISC-Pipeline

A 16-bit RISC Processor, with a four stage pipeline

Language: Verilog - Size: 327 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

edd-ie/Elevator-Simulator

An elevator simulator written in MIPS assembly language

Language: Assembly - Size: 3.88 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

0HugoHu/Harry-Potter-Strategy-Game

Duke ECE 651: Software Engineering Final Project. RISC: Really Interesting Strategic Conquest. ECE651; Duke ECE651;

Language: Java - Size: 533 MB - Last synced at: 2 days ago - Pushed at: about 1 year ago - Stars: 7 - Forks: 0

SoCXin/TLSR8258

L1 R1: Telink 48MHz BLE SoC (TLSR8258/TLSR8253/TLSR8251)

Language: C - Size: 10.2 MB - Last synced at: about 1 month ago - Pushed at: about 2 years ago - Stars: 18 - Forks: 4

KietLe11/KLP32-RISCV

This project implements a simple RISC-V processor for FPGAs. It supports the RV32I base instruction set and is designed for educational and experimental purposes.

Language: Verilog - Size: 407 KB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 4 - Forks: 0

fish4terrisa-MSDSM/archriscv-term

A app to run Arch Linux riscv64 on android using RVVM

Language: Java - Size: 45.5 MB - Last synced at: about 1 month ago - Pushed at: 2 months ago - Stars: 22 - Forks: 1

tvlad1234/toymcu

Verilog implementation of a microcontroller, using the (extended) Princeton TOY ISA

Language: Verilog - Size: 120 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

TimoSalomaki/EmotionEngineDisassembler

WIP disassembler capable of disassembling machine code of PlayStation 2's Emotion Engine CPU (TX79)

Language: C# - Size: 23.2 MB - Last synced at: 4 days ago - Pushed at: about 5 years ago - Stars: 9 - Forks: 1

firelink-library/arch

Material educacional sobre arquitetura de computadores.

Language: TypeScript - Size: 4.1 MB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 2

platformio/platform-shakti

Shakti: development platform for PlatformIO

Language: Python - Size: 638 KB - Last synced at: 18 days ago - Pushed at: almost 3 years ago - Stars: 30 - Forks: 10

wdevore/RISCV-Meta-Assembler

RISC-V meta assembler that adds quality of life features to assembly

Language: Go - Size: 34.2 KB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

dexterfloreza/COE608

COE608 Computer Organization and Architecture Repository.

Language: VHDL - Size: 7.86 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

szym-mie/2mach

Unifinished project of 2-instruction virtual machine and assmbler in C

Language: C - Size: 17.6 KB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

tasmirz/Computer

A 29bit , 5 Stage pipelined RISC computer with dedicated assembler.

Language: Jupyter Notebook - Size: 3.21 MB - Last synced at: about 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

fzipp/oberon

Project Oberon RISC emulator in Go

Language: Go - Size: 219 KB - Last synced at: about 1 month ago - Pushed at: 4 months ago - Stars: 57 - Forks: 4

SKpro-glitch/Shorthand-RISC

This is a simplified assembly language with a tabular structured instruction set. This is meant for easy learning and fast implementation of assembly languages in microprocessors and microcontrollers. - Soham Kapur, VIT Chennai

Language: Java - Size: 22.5 KB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

darklife/udarkrisc

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

Language: Verilog - Size: 1.97 MB - Last synced at: 2 months ago - Pushed at: almost 2 years ago - Stars: 14 - Forks: 3

cgyurgyik/riscv-assembly

Implementation of common functions using RISC-V assembly.

Language: Assembly - Size: 79.1 KB - Last synced at: about 1 month ago - Pushed at: over 5 years ago - Stars: 14 - Forks: 3

Kaweees/ViperASM

An assembler for RISC-V (RV32I) written in Go (🚧 in construction 🚧)

Language: Go - Size: 227 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

schorrm/arm2riscv

Arm AArch64 to RISC-V Transpiler

Language: Python - Size: 2.34 MB - Last synced at: 29 days ago - Pushed at: almost 5 years ago - Stars: 33 - Forks: 3

710lucas/RISC-I-Emu

A simple emulator based on the Berkeley RISC (RISC-I) created by David A. Patterson | Um simples emulador do Berkeley RISC (RISC-I) criado por David A. Patterson

Language: C++ - Size: 98.6 KB - Last synced at: 15 days ago - Pushed at: 4 months ago - Stars: 2 - Forks: 0

michaeljclark/riscv-meta

RISC-V Instruction Set Metadata

Size: 39.1 KB - Last synced at: about 1 month ago - Pushed at: over 6 years ago - Stars: 41 - Forks: 11

mongrelgem/RISCY

Simple RISC-V RV32I CPU in VHDL for use in FPGA Designs

Language: VHDL - Size: 395 KB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 13 - Forks: 4

pdaxrom/microcpu

16 bit microprocessor for FPGA

Language: Assembly - Size: 1.66 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 2 - Forks: 2

jasonhsu93/CPU-Classic-RISC-Pipeline-Machine

Made a fully functional CPU model capable of performing essential computing tasks, such as executing instructions from memory, handling data with load and store operations.

Language: SystemVerilog - Size: 48.8 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Inspiaaa/Micro8

An 8-bit RISC computer built in Digital with a custom ISA and general-purpose assembler.

Language: Java - Size: 5.74 MB - Last synced at: about 1 month ago - Pushed at: 4 months ago - Stars: 4 - Forks: 0

thomasafroo/Simple-RISC-Machine

Implements a RISC processor that executes a set of ARMv7 instructions.

Language: SystemVerilog - Size: 420 KB - Last synced at: about 2 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Henrywwg/ece552

Semester project for ECE552 at UW-Madison implementing WISC-F24 ISA in Verilog. (Made public after semester finished)

Language: Assembly - Size: 28.4 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

QuorumComp/rc800

RC8xx processor family

Language: Scala - Size: 262 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 4 - Forks: 0

ben-marshall/croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

Language: SystemVerilog - Size: 754 KB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 44 - Forks: 7

DosWorld/o0c

Oberon-0 Compiler in C for MS-DOS

Language: C - Size: 203 KB - Last synced at: about 1 month ago - Pushed at: about 2 years ago - Stars: 4 - Forks: 1

danielfspencer/blizzard-4

Blizzard 4 is a 16-bit computer I designed. This repo contains the compiler, assembler and emulator needed to develop and test programs for it. Try online at:

Language: JavaScript - Size: 7.94 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 5 - Forks: 0

mrisc32/mrisc32 📦

MRSIC32 ISA documentation and development

Language: TeX - Size: 2.31 MB - Last synced at: 24 days ago - Pushed at: over 1 year ago - Stars: 90 - Forks: 9

djipi/Jwarn

Atari Jaguar wait states warning generator

Language: C - Size: 35.2 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0

rtbnb/SixteenShadesOfCpu

A 16-bit RISC CPU implemented in VHDL on an Arty A7-35T development board

Language: VHDL - Size: 258 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

lxp32/lxp32-cpu

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Language: Assembly - Size: 3.4 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 59 - Forks: 13

RaconJS/0xmin

things for the 0xmin computer. full 0xmin IDE with compiler, emulator, syntax highlighting. Language uses high-level macro language and an assembly language.

Language: Assembly - Size: 2.28 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

ulx3s/ulx3s.github.io

community projects that can be used with the ULX3S FPGA ESP32 board

Size: 2.66 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 15 - Forks: 4

wyvernSemi/mico32

LatticeMico32 instruction set simulator project

Language: C++ - Size: 12.3 MB - Last synced at: 28 days ago - Pushed at: 6 months ago - Stars: 9 - Forks: 3

nk12U/4-Stage-Pipeline-16bit-CPU

4 Stage Pipeline 16bit CPU

Language: VHDL - Size: 109 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

liuqdev/8-bits-RISC-CPU-Verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

Language: Verilog - Size: 7.08 MB - Last synced at: 6 months ago - Pushed at: over 6 years ago - Stars: 135 - Forks: 42

fyvonnet/AdventOfCode-2023-Assembly

Advent of Code 2023 solutions in RISC-V assembly.

Language: Assembly - Size: 132 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 4 - Forks: 0

GuiDev115/risc-implementation

implementarion of a cpu risc

Language: C++ - Size: 802 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

jeanthom/VR88M

Disassembler for V8 microRISC architecture.

Language: C - Size: 4.88 KB - Last synced at: 2 months ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 0

Kaweees/RivoGo

A virtual machine for a 32-bit RISC-V CPU Core (RV32I) written in Go (🚧 in construction 🚧)

Language: Go - Size: 1.59 MB - Last synced at: 2 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

Sambhav-Gautam/16-Bit-RISC-ISA-Design-Simulator

Design a 16-bit RISC ISA with 6 encoding types, covering a range of operations, including arithmetic, logic, and control, with an assembler simulator.

Language: Python - Size: 5.86 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

robotman2412/PX16

Pixie 16, taking RISC to the extreme.

Language: C++ - Size: 14.8 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

710lucas/RISC-I-Compiler-web

A web version of the RISC-I compiler

Language: JavaScript - Size: 10.7 KB - Last synced at: 3 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

supragya/mozak-vm Fork of 0xmozak/mozak-vm

RISC-V 32-bit ZK virtual machine with conditional ZK proofs & proofs aggregation via STARKY / PLONKY2

Language: Rust - Size: 6.24 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

ustb-owl/Uranus

Uranus MIPS processor by MaxXing & USTB NSCSCC team

Language: Verilog - Size: 8.4 MB - Last synced at: 9 months ago - Pushed at: over 5 years ago - Stars: 35 - Forks: 11

710lucas/RISC-I-Compiler

Um compilador simples para o meu projeto de emulador de RISC-I

Language: Java - Size: 8.79 KB - Last synced at: 3 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

spider-tronix/VLSI 📦

RISC V core implementation using Verilog.

Language: Verilog - Size: 1.53 MB - Last synced at: 9 months ago - Pushed at: about 4 years ago - Stars: 22 - Forks: 4

Related Keywords

risc 255 risc-v 58 cpu 57 verilog 44 fpga 36 processor 36 assembly 33 assembler 32 computer-architecture 29 vhdl 27 isa 22 riscv 21 mips 20 emulator 19 simulator 18 risc-processor 18 pipeline 18 virtual-machine 17 c 16 processor-architecture 13 compiler 12 architecture 11 riscv32 11 arm 10 hardware 9 cpp 8 microprocessor 8 simulation 8 instruction-set-architecture 7 systemverilog 7 mips-assembly 7 16-bit 7 rust 7 logisim 6 assembly-language 6 asm 6 alu 6 python3 6 riscv64 6 education 6 rtl 5 emulation 5 linux 5 verilog-project 5 microcontroller 5 soft-core 5 hdl 5 disassembler 5 vm 5 riscv-simulator 5 interpreter 5 computer 5 8-bit 5 design 4 python 4 x86 4 risc-v-assembly 4 cache 4 risc-i 4 custom 4 rv32i 4 open-source 4 microarchitecture 4 8bit 3 cisc 3 verilog-hdl 3 embedded 3 atmega 3 quartus 3 microcontrollers 3 go 3 c-plus-plus 3 vivado 3 armv7 3 oberon 3 qt 3 javascript 3 32-bit 3 verilator 3 riscv-emulator 3 parser 3 pipelined-processors 3 pipeline-processor 3 soc 3 university 3 8-bit-computer 3 cpu-model 3 platformio 3 64-bit 3 rars 3 xilinx 3 thesis 3 berkeley-risc 3 branch-prediction 3 fpga-programming 3 low-level 3 cpu-emulator 3 disassembly 3 core 2 processor-design 2