RascalFoxfire/Picowizard

A tiny 8 bit RISC ISA for on-chip/on-FPGA management purposes

Language: SystemVerilog - Size: 50.8 KB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 2 - Forks: 0

wyvernSemi/riscV

Open source ISS and logic RISC-V 32 bit project

Language: C++ - Size: 72.2 MB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 50 - Forks: 14

mrLSD/riscv-fs

F# RISC-V Instruction Set formal specification

Language: F# - Size: 148 KB - Last synced at: 22 days ago - Pushed at: 8 months ago - Stars: 282 - Forks: 14

maikmerten/spu32

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Language: C - Size: 714 KB - Last synced at: about 1 month ago - Pushed at: almost 3 years ago - Stars: 69 - Forks: 13

mikeroyal/RISC-V-Guide

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

Language: Assembly - Size: 1.07 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 566 - Forks: 47

KUNAL-KUMAR-SINGH-Coder/RV32I

Sapphire SoC: RV32I RISC-V core optimized for FPGAs, featuring UVM verification, AXI4-Lite bus, FreeRTOS support, and Shakti-inspired design. Open-source under MIT license for embedded/IoT applications.

Language: Verilog - Size: 111 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

SKpro-glitch/Shorthand-RISC

This is a simplified assembly language with a tabular structured instruction set. This is meant for easy learning and fast implementation of assembly languages in microprocessors and microcontrollers. - Soham Kapur, VIT Chennai

Language: Java - Size: 22.5 KB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

suyashmahar/RISC-processor

Simple single cycle RISC processor written in Verilog

Language: Verilog - Size: 149 KB - Last synced at: 3 days ago - Pushed at: about 7 years ago - Stars: 48 - Forks: 7

lxp32/lxp32-cpu

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Language: Assembly - Size: 3.4 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 59 - Forks: 13

TamaGo-HQ/cave_cpu

a primitive cavecpu for primitive cavemen

Size: 0 Bytes - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

alirezakay/RISC-CPU

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Language: VHDL - Size: 2.52 MB - Last synced at: about 2 months ago - Pushed at: almost 4 years ago - Stars: 27 - Forks: 5

jofrfu/HAW-V

Fork of a RISC-V compliant CPU, which originated in a project at the HAW Hamburg

Language: VHDL - Size: 31.9 MB - Last synced at: 7 days ago - Pushed at: about 6 years ago - Stars: 5 - Forks: 3

GabrielGiurgica/8-bit-MIPS-Processor

A Verilog implementation of an 8-bit MIPS processor

Language: Verilog - Size: 589 KB - Last synced at: 9 months ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

thenamangoyal/RISC-Simulator

A C++ pipeline based simulator of RSIC architecture.

Language: C++ - Size: 431 KB - Last synced at: 10 months ago - Pushed at: almost 5 years ago - Stars: 7 - Forks: 1

barrettotte/Subarashii-CPU

A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.

Language: Verilog - Size: 10.5 MB - Last synced at: about 1 month ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 1

meeeeet/5-Stage-Pipelined-RISC-V-Processor

Language: Verilog - Size: 4.59 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

teivah/ettore 📦

A RISC-V virtual processor, written in Rust.

Language: Rust - Size: 82 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 18 - Forks: 1

Fiser12/Procesador-Segmentado

Procesador RISC segmentado creado con Proteus con Unidad de control, 5 segmentos, corrección de errores mediante unidad de detección de conflictos (DC) y ALU.

Size: 1.88 MB - Last synced at: about 1 year ago - Pushed at: almost 9 years ago - Stars: 3 - Forks: 0

akastoras/riscv

RISC-V implementation for Parallel Computer Architecture class.

Language: Assembly - Size: 2.01 MB - Last synced at: 6 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 1

TalesNogueira/Compiler-C-Minus

C- compiler made for a unicycle processor based on MIPS with RISC instruction set. / Compilador de C- feito para um processador unicíclico baseado em MIPS com conjunto de instrução RISC. / FLEX | YACC-Bison

Language: Lex - Size: 5.86 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

xerpi/sisa-emu

SISA Architecture Emulator

Language: C - Size: 47.9 KB - Last synced at: 2 months ago - Pushed at: almost 9 years ago - Stars: 3 - Forks: 0

algorhtym/mips-pipelined-processor

A digital design project for a MIPS Reduced Instruction Set Computer (RISC) pipelined processor design that has a 5 stage basic pipeline and supports 32-bit MIPS instructions with an 8-bit wide datapath, on a 256x32 ROM and 256x8 RAM, implemented through structural VHDL

Language: VHDL - Size: 10.5 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

KonstantinosVasilopoulos/aueb_processor

A 16 bit processor, following the RISC architecture. Made with Quartus and VHDL.

Language: HTML - Size: 17.6 MB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

Alikberov/Koyaanisqatsi

Just bytes «B1 BC 2A C3 CB 4E» as «B₁ B,C ₂Add; C₃ C,B ₄Eor» is «Add B₁,C₂; Eor C₃,B₄» immediate with TTL-Circuit with 2 ticks per operation…

Language: HTML - Size: 8.12 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 0

gingerkirsch/risc-emulator-workshop

Workshop to create basic risc processor, technologies: scala, scala-js, electron.

Language: JavaScript - Size: 16.6 KB - Last synced at: over 1 year ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 1

ekaakurniawan/sp2004

32-bit RISC Processor Implemented on FPGA

Language: VHDL - Size: 3.04 MB - Last synced at: over 1 year ago - Pushed at: almost 8 years ago - Stars: 0 - Forks: 0

christinojacob/RISC-TILE64-ARCHIETECTURE

RISC TILE64 implementation in python

Language: Python - Size: 2.93 KB - Last synced at: over 1 year ago - Pushed at: about 8 years ago - Stars: 1 - Forks: 0

TeamCM/Atom-Fluorine

A RISC processor

Language: JavaScript - Size: 29.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 1

TeamCM/Atom-Processor 📦

A RISC processor

Language: JavaScript - Size: 25.4 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

rmohashi/Mips

MIPS processor implementation in VHDL

Language: VHDL - Size: 92.8 KB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 0 - Forks: 1

Kashyap682/16-bit-processor-assembler

Python code for 16- bit processor assembler and simulator.

Language: Python - Size: 49.8 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 1

adityagupta1089/Functional-Simulator-For-Simple-RISC

Functional/Pipeline Simulator for simpleRISC processor

Language: C - Size: 128 KB - Last synced at: almost 2 years ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 0

0xgirish/multiprocessorSimpleRisc

Assembler and Simulator for multiprocessor SimpleRisc ISA

Language: C++ - Size: 182 KB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 0

SarthakNijhawan/Microprocessor-EE337

IITB-RISC and RISC pipeline

Language: VHDL - Size: 149 MB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0

adamlkl/Computer-Architecture-II

Language: C++ - Size: 16.3 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

SamEThibault/elec-374

Verilog CPU Design Project, ELEC 374 - Digital Systems Engineering

Language: Verilog - Size: 223 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

djzenma/RV32IC-CPU

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

Language: Verilog - Size: 3.19 MB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 11 - Forks: 2

ic-lab-duth/DRIM4HLS

DUTH RISC V Microprocessor for High Level Synthesis

Language: C++ - Size: 15.6 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 4 - Forks: 0

dreaqdp/riscv-multiprocessor

RISC-V multiprocessor adapted to a Spartan 7 Xilinx FPGA. It is a MA - MIRI (FIB) project

Size: 2.12 MB - Last synced at: 2 months ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

Luca-Dalmasso/DLX

RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor

Language: Verilog - Size: 16.3 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 1

mrLSD/riscv-cpu

RISC-V five stage pipline CPU

Language: SystemVerilog - Size: 6.84 KB - Last synced at: 3 months ago - Pushed at: almost 6 years ago - Stars: 5 - Forks: 0

BrunoBMoura/BM_CORE

Single-cycle MIPS-based processor architecture, designed as the final project for the Laboratory of Computer Architecture and Organization course and later enhanced for both Laboratory of Operational Systems and Laboratory of Computer Networks courses.

Language: Verilog - Size: 6.14 MB - Last synced at: about 2 years ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 1

denishoornaert/ELECH473

Language: C - Size: 1.73 MB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 0

franout/DLX_project

Deluxe RISC processor

Language: VHDL - Size: 132 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 0

sudhamshu091/Single-Cycle-Risc-Pipelined-Processor-Verilog

Single Cycle MIPS Pipelined Processor using Verilog

Language: Verilog - Size: 915 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

emmapaczkowski/ELEC374

The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.

Language: Verilog - Size: 115 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 3

sudhamshu091/RISC-Processor-32-bit-Verilog

32 bit RISC Processor

Language: Verilog - Size: 231 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0

sudhamshu091/Single-Cycle-Risc-Processor-32-bit-Verilog

Single Cycle RISC MIPS Processor

Language: Verilog - Size: 570 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 13 - Forks: 1

ash-olakangal/RISC-V-Processor

Verilog implementation of multi-stage 32-bit RISC-V processor

Language: Verilog - Size: 138 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 16 - Forks: 9

xor-shift/GOR2VM

A R216 virtual machine (or emulator) written in Golang

Language: Go - Size: 43 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

sotheanithsok/Pipeline-ARM-Processor 📦

A semester-long design of pipeline arm processer using RISC instruction set.

Language: C - Size: 7.13 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

hcyang99/rv32-core

Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.

Language: SystemVerilog - Size: 74.3 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 2

Pyrix25633/risc-sim

A simple and fast interpreter for ReducedInstructionSetComputer Assembly

Language: C - Size: 7.02 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

meetdoshi90/8-Bit-RISC-Microprocessor

An 8-bit RISC based processor designed in verilog with x86 instructions.

Size: 1.85 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 1

harshalmittal4/24-bit-RISC-Processor

Computer Architecture-MIPS Processor simulation in verilog with self developed ISA

Language: Verilog - Size: 712 KB - Last synced at: 2 months ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

NayanaBannur/8-bit-RISC-Processor

A Verilog RTL model of a simple 8-bit RISC processor

Language: Verilog - Size: 146 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 5 - Forks: 2

Gluncho/Assembly-Emulator

This is an assembly emulator written in C++ language.

Language: C++ - Size: 343 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0

NaniteFactory/Elevator-with-Atmega128

A small elevator control system that runs on ATMEL's 8-bit microcontroller.

Language: C - Size: 12.7 KB - Last synced at: about 1 month ago - Pushed at: about 8 years ago - Stars: 2 - Forks: 0

Andrew-Hany/FemtoRV32-Piplined-Processor

The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.

Language: Verilog - Size: 19.5 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1

gogolB/riscy-adventure

Language: Scala - Size: 28.3 KB - Last synced at: about 2 months ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0

arunabh98/microprocessor-project

Multicycle and pipeline implementations for a RISC architecture in VHDL - EE309 Autumn 2017, IIT Bombay

Language: VHDL - Size: 1.42 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

parshwa1999/NTP-Microprocessor

A real time Microprocessor impemented in verilog and tested on Xilinx Artix FPGA.

Language: VHDL - Size: 5.18 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 2

SConsul/RISC-Microprocessor-Design

VHDL implementation of multicycle and pipelined RISC architecture - EE309 Autumn 2018, IIT Bombay

Language: VHDL - Size: 8.42 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 1

markus-k/mini-risc

A minimal 16 bit RISC CPU written in VHDL

Language: VHDL - Size: 65.4 KB - Last synced at: 6 days ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0

JagratPatkar/RISC-V

A RISC-V CPU Core of Base RV32I ISA implemented in TL-Verilog.

Size: 15.6 KB - Last synced at: 6 months ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

0xHericles/riscv-helpmate

RISC-V32I Helpmate

Language: JavaScript - Size: 4.37 MB - Last synced at: 5 days ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

sskender/FerRISC

RISC ARM7 Assembly

Language: OpenEdge ABL - Size: 1.13 MB - Last synced at: about 2 months ago - Pushed at: almost 7 years ago - Stars: 0 - Forks: 0

nikolapeja6/SS-Proj

School project for the SS (Sistemski Softver, en. System Software) course of my Bachelor's studies at the School of Electrical Engineering, University of Belgrade.

Language: C++ - Size: 1.04 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

shubhangb97/RISC-Processor-design

This repository is a design and implementation of the IIT-B RISC ISA

Language: VHDL - Size: 9.96 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 1

evgenabramov/MIPT-Compilers

🔧 MiniJava language compiler written in C++

Language: C++ - Size: 423 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 1

swapnilbembde/projects_ee309

A six-staged pipelined RISC processor FPGA implementation

Language: VHDL - Size: 531 KB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0

wannabeOG/CSN-221-Project

Implementation of a 24 bit RISC processor

Language: Verilog - Size: 1.28 MB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 6 - Forks: 1

gustavoisidio/montadorRISCV

Assembler for RISC-V instructions

Language: Haskell - Size: 18 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

Suchetaaa/Pipelined-Processor

EE-309 Course Project - 2

Language: VHDL - Size: 3.51 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 1

LeoCourbassier/CoreBassier

RISC processor done in verilog hdl for FPGA

Language: VHDL - Size: 75.3 MB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 0 - Forks: 0

bigdot123456/home Fork of cnrv/home

为推广RISC-V尽些薄力

Language: CSS - Size: 8.83 MB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 0 - Forks: 0

sarthi92/cpu_risc

Verilog implementation of 16-bit RISC Processor with 4-stage pipeline

Language: Verilog - Size: 51.8 KB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 1

LSantos06/SystemC_RISC16

Trabalho 4 de Modelagem de Sistemas em Silício 1/2017

Language: C++ - Size: 322 KB - Last synced at: almost 2 years ago - Pushed at: almost 8 years ago - Stars: 0 - Forks: 0