rafaelcalcada/rvx

RISC-V microcontroller IP core developed in Verilog

Language: Verilog - Size: 191 MB - Last synced at: 1 day ago - Pushed at: about 1 month ago - Stars: 174 - Forks: 22

enjoy-digital/litex

Build your hardware, easily!

Language: C - Size: 16.8 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 3,299 - Forks: 620

The-OpenROAD-Project/OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Language: Python - Size: 836 MB - Last synced at: about 10 hours ago - Pushed at: 3 months ago - Stars: 1,478 - Forks: 395

stnolting/neorv32

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Language: VHDL - Size: 225 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1,757 - Forks: 260

HEP-SoC/SoCMake

CMake based hardware build system

Language: CMake - Size: 6.06 MB - Last synced at: about 14 hours ago - Pushed at: about 15 hours ago - Stars: 19 - Forks: 3

kactus2/kactus2dev

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

Language: C++ - Size: 146 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 206 - Forks: 39

sy2002/QNICE-FPGA

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

Language: Assembly - Size: 32 MB - Last synced at: about 20 hours ago - Pushed at: 7 months ago - Stars: 72 - Forks: 17

PrincetonUniversity/ILAng

A Modeling and Verification Platform for SoCs using ILAs

Language: C++ - Size: 193 MB - Last synced at: 3 days ago - Pushed at: 10 months ago - Stars: 77 - Forks: 19

ultraembedded/riscv_soc

Basic RISC-V Test SoC

Language: Verilog - Size: 6.1 MB - Last synced at: 11 days ago - Pushed at: about 6 years ago - Stars: 122 - Forks: 30

azonenberg/antikernel

The Antikernel operating system project

Language: Verilog - Size: 8.67 MB - Last synced at: 5 days ago - Pushed at: about 5 years ago - Stars: 120 - Forks: 10

saursin/riscv-atom

An open-source 32-bit RISC-V soft-core processor

Language: C++ - Size: 2.9 MB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 34 - Forks: 15

sld-columbia/esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

Language: C - Size: 263 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 369 - Forks: 122

stnolting/neo430 📦

:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

Language: VHDL - Size: 44.3 MB - Last synced at: 22 days ago - Pushed at: over 3 years ago - Stars: 202 - Forks: 28

BigEd/XSOC-xr16

System-on-a-Chip for FPGA, with xr16 RISC core and LCC port

Language: C - Size: 3.05 MB - Last synced at: about 1 month ago - Pushed at: almost 8 years ago - Stars: 12 - Forks: 0

Choaib-ELMADI/working-with-fpga-and-vhdl

A collection of practical FPGA and VHDL projects using the ALTERA Cyclone V DE-1 SoC board.

Language: VHDL - Size: 12.4 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 4 - Forks: 0

mpskex/chisel-npu

Chisel implementation of Neural Processing Unit for System on the Chip

Language: Scala - Size: 691 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 21 - Forks: 4

maikmerten/spu32

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Language: C - Size: 714 KB - Last synced at: about 1 month ago - Pushed at: almost 3 years ago - Stars: 69 - Forks: 13

KUNAL-KUMAR-SINGH-Coder/RV32I

Sapphire SoC: RV32I RISC-V core optimized for FPGAs, featuring UVM verification, AXI4-Lite bus, FreeRTOS support, and Shakti-inspired design. Open-source under MIT license for embedded/IoT applications.

Language: Verilog - Size: 111 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

DatNguyen97-VN/cellrv32

:electron: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.

Language: SystemVerilog - Size: 8.9 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 3 - Forks: 1

meiniKi/FazyRV

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Language: SystemVerilog - Size: 772 KB - Last synced at: about 2 months ago - Pushed at: 8 months ago - Stars: 89 - Forks: 4

Atmosic/hal_atmosic

Hardware Abstraction Layer for Atmosic SoCs in the Zephyr Environment

Language: C - Size: 1.52 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 2

arm-university/Introduction-to-SoC-Design-Education-Kit

Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals

Language: HTML - Size: 28.8 MB - Last synced at: about 2 months ago - Pushed at: 10 months ago - Stars: 121 - Forks: 40

Zadielerick/soc-emulation-tutorial

An example of launching qemu, running a simple ARM or RISC-V based device and adding a custom peripheral.

Size: 6.84 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

sebastien-guerrache/doom_zynq7000

This repo is a port of doomgeneric (itself based on Chocolate Doom) on the evaluation board Digilent Zybo Z7 built around the Zynq 7000 SoC (bare metal).

Language: C - Size: 19.6 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Fleker/chipyard-viewer

An online viewer for Chipyard output files

Language: TypeScript - Size: 15.5 MB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 6 - Forks: 2

amaranth-lang/amaranth-soc

System on Chip toolkit for Amaranth HDL

Language: Python - Size: 556 KB - Last synced at: about 1 month ago - Pushed at: 7 months ago - Stars: 86 - Forks: 32

ept221/pet-on-a-chip

Senior Design

Language: Verilog - Size: 12.3 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 12 - Forks: 3

machdyne/zucker

Zucker SOC

Language: C - Size: 478 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 14 - Forks: 3

alinja/alpus_riscv_cpu

A study of soft-core CPUs for use with FPGA designs

Language: Verilog - Size: 136 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0

alinja/alpus_wb

VHDL implementation of Pipelined Wishbone B4 interconnect

Language: VHDL - Size: 13.7 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

sparkfun/ESP32_Thing

Development platform for the Espressif ESP32 WiFi/Microcontroller SoC

Size: 675 KB - Last synced at: 29 days ago - Pushed at: about 2 years ago - Stars: 74 - Forks: 20

hardware-fab/vespa

VESPA prototyping framework for FPGA-based, accelerator-oriented SoCs

Language: C - Size: 366 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

panastasiadis/soc-verification-with-cad-tools

This repository is about the main project of the course "VLSI System Design". This course is a part of the undergraduate studies of University of Thessally - ECE Department located in Volos, Greece.

Language: Verilog - Size: 8.72 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

Frank-Zeyda/esg-gdl

Embedded Systems Geeks Guadalajara - Collaboration Space

Language: C - Size: 30.4 MB - Last synced at: 5 days ago - Pushed at: 6 months ago - Stars: 1 - Forks: 1

icgrp/ese532_handouts

Course handouts for ESE532 at UPenn

Language: Shell - Size: 53.1 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 3 - Forks: 4

ZipCPU/videozip

A ZipCPU SoC for the Nexys Video board supporting video functionality

Language: Verilog - Size: 9.34 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 16 - Forks: 1

EpiSci/SoCRATES

System-on-Chip Resource Adaptive Scheduling using Deep Reinforcement Learning

Language: Python - Size: 1.78 MB - Last synced at: 8 days ago - Pushed at: over 2 years ago - Stars: 15 - Forks: 2

priyanka-p01/SoC-with-VerilogHDL-and-Verilog-conceptsheet

Documented my learnings of the System-on-Chip course using Verilog. Verilog enthusiasts interested in adding more VHDL concepts into this repository are more than welcome to fork, clone and add contributions!

Language: Verilog - Size: 8.79 KB - Last synced at: 9 months ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0

sergachev/litex-template

Template project for LiteX-based SoCs

Language: Python - Size: 199 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 17 - Forks: 5

CSharperMantle/http-parser-arduino 📦

HTTP request/response parser in C tuned for low-profile MCUs like Arduino

Language: C - Size: 822 KB - Last synced at: 12 months ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

Everloom-129/ECE385-Digital-Systems-Lab

The goal of ECE 385 course is to teach students to design, build, and test/debug a digital system, which can be a 16-bit microprocessor, a dedicated logic core, or a system-on-a-chip (SoC) platform

Language: Verilog - Size: 113 MB - Last synced at: 9 months ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0

ammrat13/fpga-playground

An FPGA-based RISC-V SoC to mess around with

Language: Verilog - Size: 39.1 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

paulchen2713/NTHU-SoC_2022

COM 5242 Introduction to SoC and its Applications 2022 Course Materials

Size: 269 MB - Last synced at: about 2 months ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

hajali-amine/stm32-workshop

Our work during the STM32 workshop that we studied at INSAT.

Language: HTML - Size: 1.34 MB - Last synced at: about 1 year ago - Pushed at: almost 4 years ago - Stars: 9 - Forks: 0

JasonBrave/MicroSoC

RISC-V SoC

Language: SystemVerilog - Size: 37.1 KB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

thainnos/FISMOS

FPGA Implementation of a Security Module as Open Source

Language: Verilog - Size: 2.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

Mark1626/litex-alchitry-cu-examples

Examples of using Litex on an Alchitry Cu board

Language: Python - Size: 72.3 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

manili/VSDBabySoC

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

Language: Verilog - Size: 11.5 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 27 - Forks: 10

Hank0626/FPGA-Game-Design

Fireboy & Water Girl in the Forest Temple implemented on an FPGA board for UIUC's ECE385 Digital Systems Laboratory.

Language: Verilog - Size: 388 MB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 24 - Forks: 0

TinyRetroWarehouse/Awesome-Retro-Docs

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

Size: 13.8 GB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 142 - Forks: 18

gergo-papp/SystemOnChip-ImageProcessing-myRIO

Image Processing Algorithms on System-on-Chip FPGA Devices using a myRIO as hardware and LabVIEW as software

Language: LabVIEW - Size: 6.27 MB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 3

mankelly/VerilogProjects

All projects that utilize the Verilog & SystemVerilog HDL's.

Language: SystemVerilog - Size: 602 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 1

mankelly/VHDLProjects

All projects that utilize VHDL.

Language: VHDL - Size: 299 KB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

gabrielganzer/SoC-VaccineRefrigerator

Firmware development for a low-cost Vaccine Refrigerator (VARE) using the STM32F407G-DISC1 Microcontroller programmed in C with PlatformIO IDE using the STM32 HAL Library and simulated with Renode™.

Language: C - Size: 21.5 KB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 0

gabrielganzer/RTSNoC-Sniffer

Non-intrusive packet delivery monitoring service for Networks-on-Chip (NoCs) focusing on real-time systems. Hardware verification and development in C++/SystemC using the Visual Studio 2017 IDE.

Language: C++ - Size: 29.3 KB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 0

stephenry/cc

A cache coherence simulator for a multiprocessor System On Chip (SOC).

Language: C++ - Size: 1020 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 1

MarcelHa97/DVB-S2-Modulator

The aim of this project is to implement a DVB-S2 Modulator on a SoC (System on Chip)

Language: VHDL - Size: 296 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

plasoc/axiplasma

AXI/MIPS SoC developed in VHDL with FreeRTOS port. Capable of running either preemptively or cooperatively.

Language: VHDL - Size: 135 MB - Last synced at: about 1 year ago - Pushed at: about 7 years ago - Stars: 7 - Forks: 1

aminjahanpour/edge_solver

Edge Solver source code running on an RV32IF RISC-V computing core, all written in Verilog

Language: Verilog - Size: 262 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

cezs/jtx1inst

A custom C API for instrumenting Jetson TX1’s SoM and SoC

Language: C - Size: 86.9 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 7 - Forks: 2

arnulfrupp/HPP-for-OpenThread

Halloween++ (H++) scripting language for microcontrollers including support for OpenThread

Language: C - Size: 1.05 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

MHesham/WinWireKm

A kernel-mode driver for exposing Linux like mmap(...) to user-mode applications on Windows for direct physical memory access.

Language: C++ - Size: 141 KB - Last synced at: about 2 years ago - Pushed at: almost 10 years ago - Stars: 3 - Forks: 3

ZipCPU/zbasic

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

Language: Verilog - Size: 3.03 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 36 - Forks: 5

JoseAmador95/UoS_RSoC 📦

Reconfigurable Systems on Chip Mini Project

Language: VHDL - Size: 53.2 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 1

JulienGrv/Zynq-TX-UTT

Project about hardware acceleration performance on a Xilinx Zynq-7000 SoC ZC702

Language: VHDL - Size: 123 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 3

mellowcandle/socfs

SOC register access via FUSE

Language: C - Size: 37.1 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

semahawk/icarium

Trying to implement a soft core SoC

Language: Verilog - Size: 559 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 4 - Forks: 0

infini8-13/riscv-ms-soc

A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier

Language: Verilog - Size: 84 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

davemuscle/camera_journey

Various lessons learned while designing an OV5640 camera display in VHDL/Embedded Linux on a Cyclone V SOC board

Language: VHDL - Size: 53.9 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

cs-t1/proto-core

Attempt at building entirely from scratch a RISC-V SoC for self-education purposes.

Language: SystemVerilog - Size: 91.8 KB - Last synced at: 3 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

BabarZKhan/ICTP-System-on-Chip-labs

Size: 0 Bytes - Last synced at: 2 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

jack994/Mastermind-with-Raspberry-Pi2

Size: 827 KB - Last synced at: 3 months ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

OValery16/TransferCL

TransferCL: an open framework for transfer learning on mobile device

Language: C - Size: 4.13 MB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 9 - Forks: 6

githubfoam/openbmc-sandbox

openbmc Baseboard Management Controller

Size: 17.6 KB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

hassan-alhujhoj/Embedded-Systems-Wacky-Races

Embedded System Design

Language: C - Size: 340 MB - Last synced at: 6 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

jeandet/SocExplorer Fork of SocExplorer/SocExplorer

This is an ongoing rewrite of https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/SocExplorer

Language: C++ - Size: 8.02 MB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 0 - Forks: 0

polymitis/mixed-signal-oscilloscope

Mixed-Signal Oscilloscope on Chip

Language: Verilog - Size: 39.6 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 1

jeandet/VHD_Lib

LPP's VHD_Lib is a kind of addon to gaisler's grlib with most Laboratory of Plasma Physics VHDL IPs.

Language: VHDL - Size: 68.1 MB - Last synced at: about 1 month ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0

polymitis/camera-soc

Camera System on Chip

Language: VHDL - Size: 51.6 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

LionOfJewdah/convolutional_neural_networks_for_Verilog_HLS

Convolutional Neural Networks for Verilog High-Level Synthesis

Size: 1000 Bytes - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0