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GitHub / LionOfJewdah / convolutional_neural_networks_for_Verilog_HLS

Convolutional Neural Networks for Verilog High-Level Synthesis

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Forks: 0
Open Issues: 0

License: mit
Language:
Repo Size: 1000 Bytes
Dependencies: pending

Created: over 5 years ago
Updated: over 5 years ago
Last pushed: over 5 years ago
Last synced: about 2 months ago

Topics: cnn, cpp, fpga, hardware-acceleration, high-level-synthesis, machine-learning, network-on-chip, neural-network, system-on-chip, verilog

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