GitHub / LionOfJewdah / convolutional_neural_networks_for_Verilog_HLS
Convolutional Neural Networks for Verilog High-Level Synthesis
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License: mit
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Size: 1000 Bytes
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Created at: over 6 years ago
Updated at: over 6 years ago
Pushed at: over 6 years ago
Last synced at: about 1 year ago
Topics: cnn, cpp, fpga, hardware-acceleration, high-level-synthesis, machine-learning, network-on-chip, neural-network, system-on-chip, verilog
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