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GitHub / stnolting / neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stnolting%2Fneorv32
Stars: 1,427
Forks: 197
Open Issues: 10
License: bsd-3-clause
Language: C
Repo Size: 194 MB
Dependencies:
8
Created: almost 4 years ago
Updated: about 1 month ago
Last pushed: about 1 month ago
Last synced: about 1 month ago
Topics: asic, asip, cpu, embedded, fpga, gdb, microcontroller, neorv32, openocd, processor, risc-v, riscv, rtl, rv32, safety, soc, soft-core, system-on-chip, verilog, vhdl
Files
Dependencies
- actions/checkout v2 composite
- actions/download-artifact v2 composite
- actions/upload-artifact v2 composite
- mattnotmitt/doxygen-action v1.2.1 composite
- VUnit/vunit_action master composite
- actions/checkout v3 composite
- actions/upload-artifact v3 composite
- docker://ghcr.io/stnolting/neorv32/sim * composite