GitHub topics: rv32im
Haoziwan/Interactive-RISC-V-Simulator
A web-based RISC-V simulator https://riscv-simulator-five.vercel.app
Language: TypeScript - Size: 601 KB - Last synced at: about 8 hours ago - Pushed at: about 9 hours ago - Stars: 1 - Forks: 0
sysprog21/shecc
A self-hosting and educational C optimizing compiler
Language: C - Size: 1.94 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1,214 - Forks: 129
jesseopdenbrouw/thuas-riscv
The THUAS RISC-V RV32IM Zicsr Zicntr Zihpm Zicond Zba Zbb Zbs Sdext Sdtrig microcontroller
Language: C - Size: 20 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 5 - Forks: 1
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
Language: Verilog - Size: 2.98 MB - Last synced at: 23 days ago - Pushed at: over 3 years ago - Stars: 980 - Forks: 164
Sudarshan0102/v
v is a lightweight, fast-paced text editor designed for Unix-like operating systems. It features a unique modal editing style and a powerful plugin system for customization.
Size: 0 Bytes - Last synced at: 29 days ago - Pushed at: 29 days ago - Stars: 0 - Forks: 0
KUNAL-KUMAR-SINGH-Coder/RV32I
Sapphire SoC: RV32I RISC-V core optimized for FPGAs, featuring UVM verification, AXI4-Lite bus, FreeRTOS support, and Shakti-inspired design. Open-source under MIT license for embedded/IoT applications.
Language: Verilog - Size: 111 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
swetland/os-workshop
Some materials and sample source for RV32 OS projects.
Language: C - Size: 5.61 MB - Last synced at: 8 days ago - Pushed at: almost 3 years ago - Stars: 22 - Forks: 0
ultraembedded/riscv
RISC-V CPU Core (RV32IM)
Language: Verilog - Size: 5.27 MB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 1,398 - Forks: 251
ultraembedded/riscv_sbc
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
Language: Verilog - Size: 2.01 MB - Last synced at: 20 days ago - Pushed at: almost 5 years ago - Stars: 29 - Forks: 4
ultraembedded/riscv-linux-boot
Trivial RISC-V Linux binary bootloader
Language: C - Size: 19.5 KB - Last synced at: 20 days ago - Pushed at: about 4 years ago - Stars: 50 - Forks: 10
cepdnaclk/e16-co502-RV32IM-pipeline-implementation-group1
The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWave was used to observe the behavior.
Language: Verilog - Size: 8.34 MB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 23 - Forks: 4
jesseopdenbrouw/riscv-rv32 📦
A synthesizable RISC-V RV32IM microcontroller written in VHDL
Language: C - Size: 14.3 MB - Last synced at: 14 days ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 0
mattbucknall-oss/rv32im-gnu-toolchain
Simple bash script for building GNU riscv32-unknown-elf-gcc newlib toolchain.
Language: Shell - Size: 34.2 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0
LockBlock-dev/Vector
RISC-V ISA emulator
Language: C++ - Size: 41 KB - Last synced at: 16 days ago - Pushed at: 3 months ago - Stars: 6 - Forks: 0
ultraembedded/minispartan6-audio
miniSpartan6+ (Spartan6) FPGA based MP3 Player
Language: Verilog - Size: 595 KB - Last synced at: about 2 months ago - Pushed at: over 5 years ago - Stars: 27 - Forks: 8
filiparag/ftn-riscv-mcu 📦
Softcore microcontroller with peripherals based on PicoRV32
Language: Verilog - Size: 459 KB - Last synced at: 3 days ago - Pushed at: 8 months ago - Stars: 2 - Forks: 0
tvlad1234/rv32adventure
Becoming acquainted with the RISC-V ISA by writing an emulator
Language: C - Size: 34.2 KB - Last synced at: 26 days ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 1
kuopinghsu/srv32
Simple 3-stage pipeline RISC-V processor
Language: C - Size: 3.44 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 125 - Forks: 23
ultraembedded/riscv-linux Fork of riscvarchive/riscv-linux
RISC-V Linux Port (supporting RV32IM - CPUs without atomic extensions)
Language: C - Size: 1.48 GB - Last synced at: 12 months ago - Pushed at: about 6 years ago - Stars: 4 - Forks: 4
ArthurFerreira2/herve
herve, the rv simulator is a simple risc-v RV32IMA ISA simulator.
Language: Assembly - Size: 1.52 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
ArvinDelavari/RV32-APX
32 Bits RISC-V Processor with Approximate Functions
Language: Verilog - Size: 140 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0
rob-ng15/Silice-Playground
Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
Language: C - Size: 640 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 34 - Forks: 5
solomspd/RISC-V-CPU
RISC-V 5-stage pipeline RV32I implementation with forwarding in verilog with drivers to work on xilinx nexus a7 FPGA boards
Language: Verilog - Size: 1.15 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0
splinedrive/TangNano-9K-example Fork of sipeed/TangNano-9K-example
TangNano-9K-example project with kianRiscV cpu
Language: GLSL - Size: 1.34 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 2
Juminiy/sysy
sysy lang by c executable in risc-v platform.
Language: Makefile - Size: 12.7 KB - Last synced at: 2 months ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
saleh1204/rv32im
RV32IM System-on-Chip (SoC)
Language: Verilog - Size: 6.44 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 1
cs-t1/proto-core
Attempt at building entirely from scratch a RISC-V SoC for self-education purposes.
Language: SystemVerilog - Size: 91.8 KB - Last synced at: 2 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
