GitHub topics: artix-7

Repositories

ultraembedded/biriscv

32-bit Superscalar RISC-V CPU

Language: Verilog - Size: 2.98 MB - Last synced at: 4 days ago - Pushed at: over 3 years ago - Stars: 1,021 - Forks: 171

ultraembedded/FPGAmp

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

Language: C - Size: 12.5 MB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 277 - Forks: 43

eonu/fpga

Hardware implementations for basic digital circuit designs in Verilog with a Xilinx Artix-7 FPGA chip on a Digilent Basys 3 development board.

Language: Verilog - Size: 2.03 MB - Last synced at: 6 days ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

chipsalliance/f4pga-xc-fasm2bels

Library to convert a FASM file into BELs importable into Vivado.

Language: Verilog - Size: 1.34 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 13 - Forks: 13

Sped0n/ada

An Artix 7 based dual channel oscilloscope.

Language: VHDL - Size: 58.2 MB - Last synced at: 7 days ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 1

qubeck78/tangerineA7_100

RISC-V based SOC for Qmtech Artix7-100 Wukong board with 720p VGA, DDR3 and cache controller

Language: VHDL - Size: 2.21 GB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 3 - Forks: 0

briansune/FPGA-Camera-MIPI-DVP-Verilog

FPGA Camera Parallel & MIPI Verilog

Size: 56.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 20 - Forks: 2

ADolbyB/vhdl-fpga-nexys-a7

A collection of code from CDA 4240C: Design of Digital System and Lab

Language: VHDL - Size: 5.58 MB - Last synced at: 2 months ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0

Bubi2001/DaedaLogic

FPGA dev board based off AMD Xilinx Artix 7 XC7A35T-1FTG256C with lots of peripherals

Size: 3.91 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

ultraembedded/usb2sniffer

USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)

Language: Verilog - Size: 1.2 MB - Last synced at: 3 months ago - Pushed at: almost 5 years ago - Stars: 55 - Forks: 11

j3soon/Handwritten-Digit-Recognition-Painter

A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.

Language: VHDL - Size: 30 MB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 22 - Forks: 5

This project implements real-time image processing on an Artix-7 FPGA using VGA display. It applies filters like negative, grayscale, and color thresholding to images stored in Block RAM. The filters are controlled via hardware switches, and the processed image is displayed on a VGA monitor.

Language: Tcl - Size: 60.5 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

vankxr/icyradio

Over-engineered SDR development board

Language: VHDL - Size: 411 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 34 - Forks: 5

afzalamu/8Bit-signed-Full-Adder-on-ARTIX-7-FPGA

Verilog code to implement 8 bit full adder and demonstration of the result on FPGA board.

Language: Verilog - Size: 11.7 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

liolok/HDU_CO_Guide

HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南

Language: Verilog - Size: 31.7 MB - Last synced at: 2 months ago - Pushed at: about 6 years ago - Stars: 14 - Forks: 1

raleighlittles/Applied_Digital_Logic_Exercises_Using_FPGAs

Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.

Language: Verilog - Size: 13.2 MB - Last synced at: 2 months ago - Pushed at: over 3 years ago - Stars: 7 - Forks: 1

LilyTronics/nexys_a7_projects

Project for the Digilent Nexus A7 development board (Xilinx/AMD Artix-7)

Language: Tcl - Size: 37.1 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

Prajjv/RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

Language: Tcl - Size: 146 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 1

whutddk/YJ432-PL-PS

ARM+FPGA borad demo

Language: C - Size: 13.9 MB - Last synced at: about 1 year ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0

FallingLights/Audio-Processing-Artix-7

Realtime Audio Processing on Artix-7 FPGA written in VHDL

Language: VHDL - Size: 113 MB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 1

7enTropy7/Artix_7

My experiments with Nexys4 DDR Artix-7 FPGA Board

Language: Verilog - Size: 31.3 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 3

whutddk/MK64F-platform

A PCB platform based on the architecture of Arm + FPGA

Language: HTML - Size: 229 MB - Last synced at: about 1 year ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 4

CodiieSB/VHDL-ArtyA7_Blinky

The code allows anyone with the Artix A7 FPGA Board to Blink the On-Board LED for any predefined Frequency.

Language: Tcl - Size: 32.2 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

briansune/Artix-7-Parallel-OV7740

Artix-7-Parallel-OV7740

Size: 289 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

briansune/Artix-7-Parallel-OV5640

Artix 7 Parallel OV5640

Size: 3.28 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

briansune/Artix-7-Parallel-OV7670

Artix-7-Parallel-OV7670

Size: 325 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

briansune/Artix-7-Parallel-OV9655

Artix-7-Parallel-OV9655

Size: 290 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

briansune/Artix-7-Parallel-OV2640

Artix-7-Parallel-OV2640

Size: 286 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

pavel-demin/usb104-a7-notes

Notes on the USB104 A7 development board

Language: Tcl - Size: 1.12 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Language: TeX - Size: 191 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

hglee/AlchitryAuFpgaExample

Alchitry Au FPGA Board Example Project

Language: SystemVerilog - Size: 4.81 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 1

hglee/Alchitry_Au_Sample_BasicDDR

Alchitry Au FPGA Board DDR Sample Project

Language: SystemVerilog - Size: 701 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

whutddk/verilogRisc

基于蜂鸟E203的魔改

Language: Verilog - Size: 47.2 MB - Last synced at: about 1 year ago - Pushed at: over 5 years ago - Stars: 6 - Forks: 3

hglee/Alchitry_Au_Sample_UART

Alchitry Au FPGA Board UART Sample Project

Language: SystemVerilog - Size: 1.24 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

hglee/Alchitry_Au_Ft_Sample_BasicWrite

Alchitry Au FPGA Board with Ft Module Basic Write Sample Project

Language: Tcl - Size: 251 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

hglee/Alchitry_Au_Ft_Sample_FIFOWrite

Alchitry Au FPGA Board with Ft Module FIFO Write Sample Project

Language: SystemVerilog - Size: 771 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Chrisdeleon91/Xilinx-Artix-7-PCIe-Project

Created project using a PCIe root-complex and endpoint on a Xilinx Artix-7.

Language: VHDL - Size: 90.8 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Mazan-ka/ps2_mouse_interface

Change the color of square on display via vga with mouse PS2 protocol

Language: Verilog - Size: 9.77 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Mario-Hero/Async-Karin 📦

Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.

Language: Verilog - Size: 446 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 29 - Forks: 5

Related Keywords

artix-7 48 fpga 34 verilog 20 vivado 12 xilinx 12 vhdl 10 hdmi 7 basys3 6 xilinx-vivado 6 ddr3 6 xilinx-fpga 5 systemverilog 5 alchitry-au 5 alchitry 5 risc-v 5 camera 5 dvp 4 hdl 4 digilent 4 fpga-programming 3 hardware 3 ft600 3 microblaze-mcs 3 xc7a35t 3 ov2640 2 ov5640 2 ov9655 2 tcl 2 nexys-a7 2 uart 2 fifo 2 ddr 2 embedded 2 image-processing 2 artix 2 vitis 2 sdr 2 verilog-project 2 cortex-m4 2 arm-fpga 2 hardware-designs 2 ov7740 1 xga 1 ov7670 1 svga 1 nexys-4-spartan-3e 1 dsp 1 usb104-a7 1 parallel-computing 1 intel-oneapi 1 axi 1 axi-lite 1 axi-memory-mapped 1 axi-stream 1 hls 1 hpc 1 compiler 1 vitis-hls 1 vivado-ip-integrator 1 vivado-vitis 1 nexus 1 c 1 flexbus 1 hw-sw-co-design 1 artix7 1 audio-processing 1 nexys4ddr 1 freescale 1 bcd-display 1 mk64 1 nxp 1 pcb 1 spi 1 artix-35t 1 led 1 ledblink 1 vhdl-examples 1 nexys4-board 1 nexys4 1 async 1 async-circuit 1 async-karin 1 saarland-university 1 matlab 1 asynchronous 1 lme 1 asynchronous-framework 1 displays 1 cyclone-iv 1 picorv32 1 picosoc 1 arty 1 basys2 1 som 1 self-organizing-map 1 kohonen-map 1 data-mining 1 data-science 1 xilinx-hls 1 xilinx-vitis 1