GitHub / ADolbyB / vhdl-fpga-nexys-a7
A collection of code from CDA 4240C: Design of Digital System and Lab
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Stars: 3
Forks: 0
Open issues: 0
License: None
Language: VHDL
Size: 5.58 MB
Dependencies parsed at: Pending
Created at: about 2 years ago
Updated at: 2 months ago
Pushed at: almost 2 years ago
Last synced at: about 1 month ago
Topics: artix-7, fpga, hardware-description-language, hdl, nexys-a7, verilog, vhdl, xilinx-vivado
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