GitHub topics: hardware-description-language
asyncvlsi/act
ACT hardware description language and core tools.
Language: C++ - Size: 4.94 MB - Last synced at: about 24 hours ago - Pushed at: 1 day ago - Stars: 110 - Forks: 27

clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
Language: Haskell - Size: 19.7 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1,501 - Forks: 161

eliainnocenti/HES-Laboratories
Laboratories for Hardware and Embedded Security Exam @ Polito - Materials and supporting documentation for the HES Labs.
Language: Verilog - Size: 158 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

Botti01/Hardware-Embedded-Security
This repository contains exercises and labs for the "Hardware & Embedded Security" course in the Master's program in Cybersecurity at Politecnico di Torino.
Language: Verilog - Size: 63.6 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

mit-plv/kami
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
Language: Coq - Size: 4.67 MB - Last synced at: 3 days ago - Pushed at: 9 months ago - Stars: 154 - Forks: 26

cong2738/May_team_project_I2C_SPI
i2c com, spi com with AMBA AXI
Language: VHDL - Size: 71.5 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 0 - Forks: 3

pc2/sus-compiler
A new Hardware Design Language that keeps you in the driver's seat
Language: Rust - Size: 17.5 MB - Last synced at: 3 days ago - Pushed at: 4 days ago - Stars: 80 - Forks: 5

pat-pgt/MultiFrequenciesDetector
Time domain to logarithmic frequency domain converter, as the polyphase FFT do for the linear.
Language: VHDL - Size: 271 KB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 1 - Forks: 0

SystemRDL/PeakRDL
Control and status register code generator toolchain
Language: Python - Size: 136 KB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 134 - Forks: 28

JulianKemmerer/PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Language: VHDL - Size: 76.4 MB - Last synced at: 16 days ago - Pushed at: 18 days ago - Stars: 653 - Forks: 51

jofrfu/tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Language: VHDL - Size: 1.42 MB - Last synced at: 12 days ago - Pushed at: over 6 years ago - Stars: 465 - Forks: 66

akhil-b-26/8bit-ALU-verilog
The project involves designing an 8-bit Arithmetic Logic Unit (ALU) using Verilog. The ALU performs eight different operations based on a 3-bit opcode, making it a fundamental component in digital circuits and processors. The implementation includes both the ALU module and a testbench to verify its functionality.
Language: Verilog - Size: 106 KB - Last synced at: 23 days ago - Pushed at: 23 days ago - Stars: 0 - Forks: 0

mit-plv/koika
A core language for rule-based hardware design 🦑
Language: Coq - Size: 4.81 MB - Last synced at: 21 days ago - Pushed at: 8 months ago - Stars: 153 - Forks: 12

RenatoMignone/Hardware_Security
This repository contains exercises and laboratories related to the Hardware and Embedded Security Course at @polito, where we mainly write code for hardware description like Verilog and VHDL
Language: Verilog - Size: 61.1 MB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 0 - Forks: 0

drom/awesome-hdl
Hardware Description Languages
Size: 135 KB - Last synced at: about 1 month ago - Pushed at: 4 months ago - Stars: 1,021 - Forks: 97

david-palma/mips-32bit
Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.
Language: VHDL - Size: 366 KB - Last synced at: 7 days ago - Pushed at: about 6 years ago - Stars: 8 - Forks: 1

cucapra/filament
Fearless hardware design
Language: Verilog - Size: 5 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 175 - Forks: 10

Pa1mantri/TCL_Scripting
TCL Script to automate the generation of Pre-layout QoR results
Language: Verilog - Size: 6.38 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

icarogabryel/flote
Flote is a HDL and Python framework for simulation. Designed to be friendly, simple, and productive. Easy to use and learn.
Language: Python - Size: 348 KB - Last synced at: 9 days ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

SystemRDL/systemrdl-compiler
SystemRDL 2.0 language compiler front-end
Language: C++ - Size: 2.53 MB - Last synced at: 27 days ago - Pushed at: 3 months ago - Stars: 251 - Forks: 70

JeffDeCola/my-verilog-examples
A place to keep my synthesizable verilog examples.
Language: Verilog - Size: 13.7 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 36 - Forks: 11

mikeroyal/VHDL-Guide
VHDL Guide
Language: VHDL - Size: 135 KB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 62 - Forks: 8

nathsou/yodl
Yet anOther hardware Description Language
Language: MoonBit - Size: 2.84 MB - Last synced at: 22 days ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

Joanna20Carrion/Joanna20Carrion
Size: 2.44 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

Anup-Naik/The-Elements-of-Computing-Systems
The solutions to projects specified in the book the elements of computing systems.
Language: Hack - Size: 15.6 KB - Last synced at: 5 days ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

broccolimicro/loom
design and verification of asynchronous circuits
Language: Python - Size: 9.93 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 21 - Forks: 0

spacetimeengineer/mupy
Python Manufacturing Utility or "mupy" is a powerful new digital-twin technology. In it's essence, a new way to think about design, physical hardware, advanced assemblies, innovative technologies, or most generally, system design.
Language: Python - Size: 65 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 12 - Forks: 2

Quanoom/FrequencyDivider
verilog code for frequency divider circuit implemented with verilog hdl
Language: Verilog - Size: 8.79 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

WangXuan95/BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
Language: Bluespec - Size: 31.1 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 566 - Forks: 44

aofarmakis/Nibbling-bits
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
Language: Verilog - Size: 4.01 MB - Last synced at: about 2 months ago - Pushed at: 6 months ago - Stars: 32 - Forks: 0

VicoHBB/Verilator-SV-Template
This project template is designed to streamline the development of SystemVerilog projects using Verilator, GTKWave, and Make. The template includes a Makefile with various recipes for compiling, simulating, and visualizing the design. It also includes a directory structure for organizing the HDL files, test benches, and simulation waveforms.
Language: SystemVerilog - Size: 62.5 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

ShabbyGayBar/VerilogAmsLib
Library of Verilog-AMS models
Size: 5.86 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

JacemHaggui/Building-a-Computer-from-Scratch
My work on the project-based course NAND2TETRIS.
Language: Assembly - Size: 4.96 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Choaib-ELMADI/getting-started-with-verilog
Getting started with Verilog: Hardware Description Language for digital design.
Language: Verilog - Size: 9.87 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 5 - Forks: 0

chaseruskin/legoHDL
An experimental package manager and development tool for Hardware Description Languages (HDL).
Language: Python - Size: 3.9 MB - Last synced at: 6 days ago - Pushed at: about 3 years ago - Stars: 14 - Forks: 2

helcsnewsxd/famaf-computer_science-computer_architecture-lab1 📦
Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
Language: SystemVerilog - Size: 2.55 MB - Last synced at: 3 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

helcsnewsxd/famaf-computer_science-computer_architecture-lab2 📦
Laboratorio 2 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
Language: Assembly - Size: 1.85 MB - Last synced at: 3 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 0

helcsnewsxd/famaf-computer_science-computer_architecture 📦
Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
Language: SystemVerilog - Size: 6.83 MB - Last synced at: 3 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 0

ADolbyB/vhdl-fpga-nexys-a7
A collection of code from CDA 4240C: Design of Digital System and Lab
Language: VHDL - Size: 5.58 MB - Last synced at: 3 months ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0

continuum5531/Computer-hardware
This project is under the "Build a modern computer from first principles:From nand to tetris part 1" course on coursera. It contains hardware parts of a computer, begenning from basic logic gates upto CPU.
Language: Assembly - Size: 121 KB - Last synced at: 21 days ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

MohammedS2lah/Digital_Design_With_VHDL
In this repository, I'll provide a simple, organized collection of VHDL designs and tutorials to help anyone learn and practice digital design using VHDL.
Language: VHDL - Size: 36.1 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Quanoom/SequenceDetector
11001 sequence detector
Language: Verilog - Size: 10.7 KB - Last synced at: about 2 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

MohammedS2lah/HDLBits_Verilog_Tutorials
Welcome to my repository, where I provide solutions to Verilog challenges from the HDLBits website
Language: Verilog - Size: 378 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

drom/reqack
🔁 elastic circuit toolchain
Language: JavaScript - Size: 275 KB - Last synced at: 10 days ago - Pushed at: 6 months ago - Stars: 30 - Forks: 5

jpt13653903/ALCHA
A New Programming Language for FPGA Projects
Language: C++ - Size: 3.99 MB - Last synced at: 4 months ago - Pushed at: 5 months ago - Stars: 6 - Forks: 0

povik/fold
high abstraction synthesis
Language: Python - Size: 765 KB - Last synced at: about 2 months ago - Pushed at: about 1 year ago - Stars: 10 - Forks: 0

GreatOdds/nand2tetris
My solutions to the nand2tetris assignments.
Language: Hack - Size: 64.5 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

agabhi017/nand2tetris
Building a modern computer from first principles. (Projects from the nand2Tetris computer systems course)
Language: C++ - Size: 31.3 KB - Last synced at: 15 days ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

cyber-anubis/The-HACK-General-Purpose-Computer
Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.
Language: Python - Size: 151 KB - Last synced at: 24 days ago - Pushed at: over 4 years ago - Stars: 99 - Forks: 5

wojciechmarek/my-fpga-journey
A set of code examples for Tang Nano 1K FPGA board.
Language: VHDL - Size: 417 KB - Last synced at: 3 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

marcotulio956/babySteps101
A compilation of several different coding challenges/exercises/drillings that I did when in my junior year. The very reason of this repo is nostalgia/documenting my first lines of code(non-projects). I might add more when seen fit.
Language: Jupyter Notebook - Size: 130 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

AkhilRai28/Single-Port-RAM
This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.
Language: Verilog - Size: 68.4 KB - Last synced at: 2 months ago - Pushed at: 10 months ago - Stars: 3 - Forks: 0

ddiogoo/nand2tetris Fork of Paganini-Thurler/nand2tetris
Building a computer from scratch to Tetris
Language: Scilab - Size: 12.6 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

shahed22/verilog-module-generator-for-state-machine
A Python-based tool for generating Verilog modules with features including customizable state machines, port definitions, and state diagrams using Graphviz. Ideal for FPGA and ASIC design workflows.
Language: Python - Size: 40 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

hsr-22/EE224_CPU-IITB
Course Project for EE224 (Digital Systems) offered in Autumn 2023
Language: VHDL - Size: 123 MB - Last synced at: 11 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

m47812/hdl_toolbox
A toolbox for automating some of the more tedious refactoring tasks comming with common HDL languages (VHDL/Verilog). Including among others: entity to instance conversion and entity cross language conversion.
Language: Python - Size: 117 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

m47812/HDL_Converter
A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.
Language: C# - Size: 366 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 6 - Forks: 2

SauravMaheshkar/verilog-template
❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)
Language: Makefile - Size: 15.6 KB - Last synced at: about 11 hours ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0

akxavier/Assignments
B.Tech CSE @ NITC
Language: C - Size: 18.6 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

kevinrvaz/HackComputer
WIP Implementation of the theoretical 16-bit computer called "Hack" based on the book "The elements of computing systems 2nd edition"
Language: Hack - Size: 725 KB - Last synced at: 11 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

tharunchitipolu/Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
Language: Verilog - Size: 19.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 32 - Forks: 6

meiniKi/logIP
Logic Analyzer IP Core
Language: SystemVerilog - Size: 306 KB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 5 - Forks: 1

EngineeringSoftware/hdlp 📦
Code and data for "On the Naturalness of Hardware Descriptions" in ESEC/FSE'20
Language: Java - Size: 40.4 MB - Last synced at: 26 days ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 2

NatsuDrag9/Kogge-Stone-Adder
Implementing a 4-bit Kogge Stone Adder (a type of carry-tree adder) in VHDL using XIlinx Vivado
Language: VHDL - Size: 19.5 KB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 2

Qyt0109/My-own-RISC-V-ISA-based-CPU-on-FPGAs
RISC-V is an open-source instruction set architecture (ISA), enabling the implementation of central processing units (CPUs) or system-on-a-chip (SoC) designs without licensing fees. This makes it highly favored among FPGA enthusiasts for softcore processor implementations.
Language: Verilog - Size: 7.18 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

gergoerdi/retroclash-lib
Library code for upcoming RetroClash book
Language: Haskell - Size: 248 KB - Last synced at: 7 days ago - Pushed at: 4 months ago - Stars: 9 - Forks: 7

Shapirogilad/Build-a-Modern-Computer-from-First-Principles-From-Nand-to-Tetris
In this project-centered course I built a modern computer system (The Hack Computer), from the ground up.
Language: Assembly - Size: 90.8 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

dlesbre/cephalopode
The cephalopod IoT processor and the bifrost compiler
Language: Haskell - Size: 315 KB - Last synced at: 2 months ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1

GSimas/INE5406
📚Repositório da Disciplina INE5406 - Sistemas Digitais
Language: HTML - Size: 341 MB - Last synced at: about 1 year ago - Pushed at: almost 7 years ago - Stars: 15 - Forks: 1

joe-legg/miniHDL
A small toy hardware description language.
Language: C++ - Size: 126 KB - Last synced at: about 1 year ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 1

metuan/ParserHDMLanguage
Parser and Lexer to Hardware Description Language using Prolog
Language: Prolog - Size: 20.5 KB - Last synced at: about 1 year ago - Pushed at: about 8 years ago - Stars: 1 - Forks: 3

fpmanna1/Architettura_dei_Sistemi_Digitali
Progetti riguardanti lo sviluppo di sistemi digitali
Language: VHDL - Size: 14.1 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Raveem13/HDLbits-practice-solution
This is a repository containing my solutions to the problem statements given on HDLBits website.
Language: Verilog - Size: 150 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

JoseIuri/Median_Filter
This implements a simple median filter on hardware.
Language: SystemVerilog - Size: 3.91 KB - Last synced at: over 1 year ago - Pushed at: almost 6 years ago - Stars: 0 - Forks: 0

jamestiotio/compstruct
SUTD 2020 50.002 Computation Structures Code Dump
Language: C - Size: 89.7 MB - Last synced at: about 1 year ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 0

Aniketkumarroy/NovaEdge32
verilog model of a 32 bit RISC-V processor core supporting the RV32I instruction set
Language: Verilog - Size: 785 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

vikrrrr/croc
ChaCha stream cipher modules written in Python, described using Amaranth.
Language: Python - Size: 19.5 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 0

VitorgsRuffo/Building-The-Hack-Computer
This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.
Language: Scilab - Size: 281 KB - Last synced at: about 1 year ago - Pushed at: almost 4 years ago - Stars: 10 - Forks: 2

AzazHassankhan/VHDLCodeCraft
Welcome to the "VHDL_Coding_Designs" repository, your gateway to the world of VHDL (VHSIC Hardware Description Language) and digital design. This is the space where hardware meets innovation, and digital concepts come to life. 🌐
Size: 182 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

FaresAtef1/AES-Advanced-Encryption-Standard
256-bit Advanced Encryption Standard Implemented with Verilog HDL.
Language: Verilog - Size: 26.4 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 2

lazyoracle/vhdl-processor
An 8-bit processor in VHDL based on a simple instruction set
Language: VHDL - Size: 209 KB - Last synced at: 12 months ago - Pushed at: over 6 years ago - Stars: 5 - Forks: 0

axvr/gait
An experimental, interactive, object-oriented, hardware description language (HDL).
Language: Clojure - Size: 33.2 KB - Last synced at: 2 days ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0

mercury-5/Verilog-HDL
Some basic hardware and logic designs and their respective testbenches written in Verilog HDL
Language: Verilog - Size: 18.6 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

ArvinDelavari/Digital-Circuits-Verilog
Sample Verilog codes for digital circuits
Language: HTML - Size: 9.31 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

fayizferosh/yosys-tcl-ui-report
5 Day TCL begginer to advanced training workshop by VSD
Language: Verilog - Size: 1.17 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 12 - Forks: 0

pawan-nirpal-031/ComputerArchitecture-MicroprocessorDesign
Basic Microprocessor Design in HDLs like Verilog.
Language: C++ - Size: 5.66 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

Eforen/FlowHS
Flow Based Hardware Simulator
Language: JavaScript - Size: 8.07 MB - Last synced at: 2 months ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 0

alizindari/FPGA-project
An implementation of mips architecture on FPGA using verilog
Language: Verilog - Size: 1010 KB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

sinjoysaha/4-bit-ripple-carry-adder
First Verilog repo.
Language: Verilog - Size: 11.7 KB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

chykon/svart
Svart is an embedded (in Dart) domain-specific language for describing binary circuits, generating a strict subset of SystemVerilog and easily interacting with external tools.
Language: Dart - Size: 81.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

vaddya/hdl 📦
Hardware Description Languages
Language: C - Size: 7.61 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

AnirudhhRamesh/BA2-DSD-TP78
Traffic Light System designed in VHDL for Digital System Design Course in EPFL BA2 (IC Section) Grade: 100%
Language: VHDL - Size: 10.8 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

AnirudhhRamesh/BA2-DSD-EV2
Yahtzee game designed in VHDL for Digital System Design Course in EPFL BA2 (IC Section) Grade: 88.89%
Language: VHDL - Size: 6.19 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

souradipp76/Digital-Design
This is digital design project written in Verilog.
Language: C - Size: 589 KB - Last synced at: almost 2 years ago - Pushed at: almost 8 years ago - Stars: 0 - Forks: 0

1brahimmohamed/Bank-Line-Machine
ELC2242 HDL project of a machine in the bank that regulates / keeps customers order
Language: Verilog - Size: 2.43 MB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

MMj4beer/nand2tetris
Building a modern computer system, from the ground up. how computers work, and how they are designed.
Language: Hack - Size: 258 KB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

lorenzozaccomer/iterative-multiplier
Project for Electronic Calculators course.
Language: VHDL - Size: 4.77 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

tilk/yieldfsm
YieldFSM, a DSL for describing finite state machines in Clash
Language: Haskell - Size: 274 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 8 - Forks: 0

aesthet1c0der/Verilog-projects
ALU (Arithmetic and Logic Unit), Ripple carry adder, Half adder and full adder are designed using all 3 styles (structural, behavioral, dataflow) and tested by generating stimulus using testbench
Language: Verilog - Size: 21.5 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0

HaoAsakura09/Nand2Tetris
the step-by-step journey of building a complete computer system from logic gates to a high-level language.
Language: Scilab - Size: 15.6 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
