GitHub topics: opentimer
Pa1mantri/TCL_Scripting
TCL Script to automate the generation of Pre-layout QoR results
Language: Verilog - Size: 6.38 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0
fayizferosh/yosys-tcl-ui-report
5 Day TCL begginer to advanced training workshop by VSD
Language: Verilog - Size: 1.17 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 12 - Forks: 0
vsdip/vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).
Language: Coq - Size: 13.1 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 7 - Forks: 1
