GitHub topics: vlsi-physical-design

Repositories

BegangLive/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: Stata - Size: 20.5 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1 - Forks: 0

limbo018/DREAMPlace

Deep learning toolkit-enabled VLSI placement

Language: C++ - Size: 18 MB - Last synced at: 5 days ago - Pushed at: 28 days ago - Stars: 798 - Forks: 219

ganeshgore/spydrnet-physical

This is a SpyDrNet Plugin for a physical design related transformations

Language: Python - Size: 18.7 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 11 - Forks: 4

lip6/coriolis

Coriolis VLSI EDA Tool (LIP6)

Language: C++ - Size: 94.3 MB - Last synced at: 3 days ago - Pushed at: 9 days ago - Stars: 65 - Forks: 11

luarss/awesome-conference-dates

VLSI Conference Dates

Language: Python - Size: 11.9 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0

AUCOHL/DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

Language: Verilog - Size: 47 MB - Last synced at: 1 day ago - Pushed at: 11 months ago - Stars: 145 - Forks: 33

lip6/alliance

Alliance VLSI CAD Tools (LIP6)

Language: C - Size: 32 MB - Last synced at: 7 days ago - Pushed at: 3 months ago - Stars: 13 - Forks: 2

TobiasKaiser/pydesignflow

Micro-Framework for FPGA / VLSI Design Flow in Python

Language: Python - Size: 87.9 KB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 4 - Forks: 3

ruisizhang123/PD_WM_GNN

[MLCAD'24] Automated Physical Design Watermarking Leveraging Graph Neural Networks & [TCAD'25] ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection

Language: C++ - Size: 87.8 MB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 1

en9inerd/SimAn

Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”

Language: C++ - Size: 4.46 MB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 12 - Forks: 2

jnestor/CADApps

VLSI CAD Algorithm Visualizations implemented as Java Applications

Language: Java - Size: 1.41 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 15 - Forks: 4

OpenTimer/Parser-Verilog

A Standalone Structural Verilog Parser

Language: Verilog - Size: 6.29 MB - Last synced at: 5 months ago - Pushed at: about 3 years ago - Stars: 85 - Forks: 34

himanshurawat443/VSD-SoC-PD-Oct-2024

2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE/Sky130)

Size: 61.5 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

amitops2103/NASSCOM_VSD_SoC_Physical_Design_Program

Digital VLSI Soc-Physical Design (Picorv32)

Size: 27.9 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 3 - Forks: 0

SalomeDevkule7/Carry-Select-Adder-8-bit

VLSI Physical Design

Size: 271 KB - Last synced at: 5 months ago - Pushed at: almost 7 years ago - Stars: 5 - Forks: 1

broccolimicro/ruler

Design rule checker for VLSI layouts

Language: Makefile - Size: 102 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

Entries for the 2023 5th National College Student Integrated Circuit EDA Elite Challenge. SoC chip physical layout static IR drop prediction project based on methods such as image processing and NLP unsupervised learning.

Language: Python - Size: 632 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 1

OpenTimer/OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

Language: Verilog - Size: 329 MB - Last synced at: 10 months ago - Pushed at: almost 2 years ago - Stars: 538 - Forks: 146

OpenTimer/Parser-SPEF

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

Language: C++ - Size: 63.4 MB - Last synced at: 10 months ago - Pushed at: almost 3 years ago - Stars: 50 - Forks: 23

srgrr/CellRouter

A SAT-Based cell router.

Language: C++ - Size: 28 MB - Last synced at: 29 days ago - Pushed at: over 6 years ago - Stars: 7 - Forks: 1

the-pinbo/EC302-VLSI-Design-Lab

EC302-VLSI-Design-Lab

Language: Roff - Size: 4.3 MB - Last synced at: 12 minutes ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

ShyamRazesh/DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING

2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)

Size: 249 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

neeraj1397/A-Primer-For-Physical-Design-Automation

This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.

Language: Jupyter Notebook - Size: 782 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 1

meeeeet/RTL-to-GDS-Implementation-of-SerDes

Language: Verilog - Size: 4.91 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 1

jnestor/MazeRouterApp

Visualization of VLSI Maze Routing Algorithms (Lee, Hadlock, A*)

Language: Java - Size: 76.2 KB - Last synced at: 3 months ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 1

VardhanSuroshi/VLSI-ASIC-Design-Flow

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

Language: Verilog - Size: 2.93 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

erihsu/Paper_Reproduction

reproduction paper research in low voltage clock tree design

Language: Perl - Size: 14.4 MB - Last synced at: about 1 year ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 3

luckyrantanplan/nthu-route

VLSI EDA Global Router

Language: C++ - Size: 11.6 MB - Last synced at: about 1 year ago - Pushed at: over 7 years ago - Stars: 57 - Forks: 12

Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

Domain Specific Hardware Accelerators - VLSI CAD Project

Language: Bluespec - Size: 4.59 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 2

harshithsn/Universal-Shift-Register

This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.

Language: Verilog - Size: 128 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 7 - Forks: 1

fayizferosh/yosys-tcl-ui-report

5 Day TCL begginer to advanced training workshop by VSD

Language: Verilog - Size: 1.17 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 12 - Forks: 0

cuhk-eda/dr-cu

Dr. CU, VLSI Detailed Routing Tool Developed by CUHK

Language: C++ - Size: 6.37 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 110 - Forks: 34

miwucy/VLSI-PDA

The course "NTHU VLSI System Design and Implementation"

Language: Prolog - Size: 59.4 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

virginrobotics/5-Stage-2.92-Ghz-CMOS-VCO

This is a documentation of the steps involved in designing a VCO on the SYNOPSYS Custom Compiler - 28nm PDK

Size: 2.57 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 7 - Forks: 0

shariethernet/Physical-Design-with-OpenLANE-using-SKY130-PDK

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified

Language: Verilog - Size: 44.9 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 26 - Forks: 7

srfunksensei/VLSI

Two Address Instructions (16bit) CPU

Language: VHDL - Size: 675 KB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 4 - Forks: 0

karthik-r-rao/VLSI_Physical_Design_Tool

A simple tool to demonstrate the physical design steps of VLSI Design Flow.

Language: Python - Size: 890 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 5 - Forks: 3

chengengjie/salt

Steiner Shallow-Light Tree for VLSI Routing

Language: C++ - Size: 2.31 MB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 30 - Forks: 5

ieee-ceda-datc/RDF-2019

DATC RDF

Language: Verilog - Size: 74.4 MB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 38 - Forks: 11

twweeb/VLSI-Physical-Design-Automation

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

Language: C++ - Size: 57.3 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 22 - Forks: 10

jinwookjungs/lefdef_util

A LEF/DEF Utility.

Language: Prolog - Size: 33.7 MB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 18 - Forks: 10

aasthadave9/Advanced-Physical-Design-Using-OpenLANE-Sky130

This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130

Size: 467 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 7 - Forks: 6

ShonTaware/OpenSource_Physical_Design

This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

Size: 4.96 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 11 - Forks: 15

AngeloJacobo/OpenLANE-Sky130-Physical-Design-Workshop

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

Size: 1.3 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 8 - Forks: 4

UdayaShankarS/TCL-Scripting

Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference

Language: Tcl - Size: 144 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 1

hibagus/64pointFFTProcessor

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

Language: Verilog - Size: 29.8 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 13 - Forks: 7

enzoleo/RePlAce Fork of The-OpenROAD-Project/RePlAce

A customized placer based on the RePlAce global placement tool.

Language: C++ - Size: 92.9 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 1

Related Keywords

vlsi-physical-design 58 vlsi 27 eda 16 vlsi-design 10 vlsi-circuits 8 vlsi-placement 7 verilog 7 vlsi-cad 6 electronic-design-automation 5 asic-design 5 open-source 4 openlane-flow 4 sky130 4 asic 4 openlane 4 python3 3 routing 3 static-timing-analysis 3 cad 3 placement 3 vlsi-project 3 rtl2gds 3 cadapplets 3 lafayette-cadapps 3 cpp17 3 computer-aided-design 3 vlsi-routing 2 vlsi-floorplan 2 soc-design 2 two-way-min-cut 2 physical-layout-analysis 2 physical-design-automation 2 nthu 2 global-placement 2 fixed-outline 2 design-automation 2 sta 2 graph-algorithms 2 magic 2 ngspice 2 vlsi-pda 2 openroad 2 cadapps 2 visualization 2 risc-v 2 linux 2 hardware 2 hardware-designs 2 circuit 2 rtl 2 layout 2 simulated-annealing 2 circuits 2 design-flow 2 electronics-engineering 2 shell-scripting 1 electric-vlsi 1 bar2308tt 1 180nm-technology 1 verilog-hdl 1 moore-machine 1 synthesis 1 moore 1 partitioning-algorithms 1 iccad 1 tcl 1 examples 1 def-parser 1 ssi 1 opentimer 1 cmos 1 hardware-description-language 1 eda-tools 1 csv 1 bash 1 universal-shift-register 1 vector-processor 1 ram 1 processor-design 1 processor-architecture 1 processor 1 inverter 1 pmos 1 lef 1 def 1 lef-parser 1 datc-rdf 1 bookshelf 1 tcl-scripts 1 digital-signal-processing 1 fast-fourier-transform 1 fpga-accelerator 1 signal-processing 1 global-routing 1 nthucs 1 gdsii 1 vlsi-design-flow 1 ic-design 1 sbcl 1 logic-synthesis 1