GitHub / VardhanSuroshi / VLSI-ASIC-Design-Flow

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/VardhanSuroshi%2FVLSI-ASIC-Design-Flow
PURL: pkg:github/VardhanSuroshi/VLSI-ASIC-Design-Flow

Topics: asic-design, openlane, opensource, risc-v, rtl, skywater, vlsi, vlsi-design, vlsi-physical-design

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• Readme
• Dependencies