GitHub topics: openlane
theopenlane/core
Core holds the central schema definitions, resolvers, endpoints, and other tooling associated with the Openlane product suite
Language: Go - Size: 49.7 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 34 - Forks: 8
mattvenn/multi_project_tools
tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
Language: Python - Size: 11 MB - Last synced at: 4 days ago - Pushed at: over 2 years ago - Stars: 36 - Forks: 14
theopenlane/riverboat
the openlane job queue server based on riverqueue
Language: Go - Size: 246 KB - Last synced at: 7 days ago - Pushed at: 10 days ago - Stars: 4 - Forks: 1
SparcLab/OpenSERDES
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
Language: Verilog - Size: 37.4 MB - Last synced at: 10 days ago - Pushed at: about 3 years ago - Stars: 159 - Forks: 33
SKpro-glitch/RISCV-Processor-ASIC
This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
Language: Verilog - Size: 138 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0
nishit0072e/openlane-flow
Openlane is a complete RTL-to-GDS flow, which uses openroad for floorplan, placement etc.
Language: Jupyter Notebook - Size: 2.89 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0
iic-jku/osic-multitool
JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
Language: Verilog - Size: 122 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 58 - Forks: 16
efabless/volare
Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
Language: Python - Size: 229 KB - Last synced at: 24 days ago - Pushed at: 26 days ago - Stars: 64 - Forks: 12
efabless/openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
Language: Python - Size: 31.4 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 272 - Forks: 54
sravani266/FlexiPacketEngine
Run the OpenLane flow to generate GDSII from the RTL using SkyWater 130nm PDK
Language: Verilog - Size: 0 Bytes - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0
SinaKarvandi/hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
Language: VHDL - Size: 46.9 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 2
krutideepanpanda/RISC-V-based-micro-controller-using-OpenLane
This is part of EC383 - Mini Project in VLSI Design.
Language: Verilog - Size: 16.6 MB - Last synced at: 8 days ago - Pushed at: about 3 years ago - Stars: 8 - Forks: 0
watbulb/tt-toolchain-build
A Linux-Local Installation of TT tools at version parity with TinyTapeout Selected Versions (see branch name)
Language: Shell - Size: 60.5 KB - Last synced at: 4 days ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0
edabk-hust/edabk_brain_soc
A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.
Language: Verilog - Size: 349 MB - Last synced at: 9 months ago - Pushed at: over 1 year ago - Stars: 33 - Forks: 6
watbulb/tt-gds-macro-testing
TinyTapeout GDS blackbox macro testing
Language: Python - Size: 186 KB - Last synced at: 4 days ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
afzalamu/NASSCOM-VSD-SOC-Design-Program
This repository contains materials and resources for a workshop on designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS).
Size: 1 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
arudeep15/NASSCOM-VSD-SOC
This Repository consists of the learnings and simulations using OpenLANE under the workshop by VSD entitled as SOC Design and Planning Workshop.
Size: 33.8 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0
aqvlsi/Openlane_Work
OpenLane Documentation
Size: 6.84 KB - Last synced at: 12 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
muhammadtalhasami/openlane
This is my openlane repository in which we perform synthesis of our design/module.
Language: Tcl - Size: 384 KB - Last synced at: 16 days ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0
KASIRGA-KIZIL/tekno-kizil
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
Language: Verilog - Size: 1.04 GB - Last synced at: 12 months ago - Pushed at: almost 2 years ago - Stars: 139 - Forks: 11
ojasvi-shah/Advanced-Physical-Design-Using-OpenLANE--Ojasvi-Shah
Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah
Size: 262 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0
Tanmay707/NASSCOM-VSD-SOC
This Repository consists of the learnings and simulations using OpenLANE under the workshop by VSD entitled as SOC Design and Planning Workshop
Size: 45.8 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
VardhanSuroshi/VLSI-ASIC-Design-Flow
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
Language: Verilog - Size: 2.93 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
harshithsn/Universal-Shift-Register
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
Language: Verilog - Size: 128 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 7 - Forks: 1
rejunity/zero-to-asic-wrapped-parallax
Tiny experimental ASIC design for efabless/OpenLane fab.
Language: Verilog - Size: 1.96 MB - Last synced at: 3 days ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 1
aasthadave9/Advanced-Physical-Design-Using-OpenLANE-Sky130
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
Size: 467 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 7 - Forks: 6
mdzakirhussain/vsdopenlaneworkshop
This is about openlane flow for ASIC Design
Size: 7.5 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0
AngeloJacobo/OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
Size: 1.3 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 8 - Forks: 4
efabless/clear_old
CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.
Language: Verilog - Size: 265 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 0
asinghani/sky130-chip-vis
Gate-level visualization generator for SKY130-based chip designs.
Language: Python - Size: 150 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 13 - Forks: 4
saathi7/Advanced-PD-using-OpenLANE-Sky130
Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
Size: 3.71 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0
Khalique13/dvsd_pe_sky130
This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral RTL of an 8-bit Priority Encoder, using SkyWater 130 nm PDK.
Language: Verilog - Size: 31.8 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 11 - Forks: 3
efabless/caravel_ibex
An example project that utilizes caravel user space for an ibex based SoC
Language: Verilog - Size: 567 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 4
kbeckmann/caravel-pll-calculator
PLL configuration generator for the Caravel management core
Language: Python - Size: 12.7 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 10 - Forks: 0
efabless/sak-deprecated
SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA
Language: Python - Size: 4.07 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 2