The-OpenROAD-Project/OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Language: Python - Size: 836 MB - Last synced at: 2 days ago - Pushed at: 16 days ago - Stars: 1,542 - Forks: 402

Pa1mantri/NASSCOM_SoC_Design

Complete RTL to GDSII flow of a picorv32a core

Size: 16.3 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

lakshmi-sathi/avsdpll_1v8

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

Size: 25.3 MB - Last synced at: 18 days ago - Pushed at: almost 4 years ago - Stars: 113 - Forks: 40

meeeeet/RTL-to-GDS-Implementation-of-SerDes

Language: Verilog - Size: 4.91 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 1

aasthadave9/Advanced-Physical-Design-Using-OpenLANE-Sky130

This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130

Size: 467 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 7 - Forks: 6

AngeloJacobo/OpenLANE-Sky130-Physical-Design-Workshop

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

Size: 1.3 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 8 - Forks: 4

heyshakya/vsd_pll

8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

Size: 8.78 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 1