GitHub topics: openram
google/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Language: Python - Size: 4.08 MB - Last synced at: 5 days ago - Pushed at: 6 months ago - Stars: 3,124 - Forks: 409
The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Language: Python - Size: 836 MB - Last synced at: 12 days ago - Pushed at: 2 months ago - Stars: 1,465 - Forks: 394
efabless/caravel
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
Language: Verilog - Size: 14 GB - Last synced at: about 1 month ago - Pushed at: 2 months ago - Stars: 319 - Forks: 82
efabless/caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Language: Verilog - Size: 3.61 GB - Last synced at: 5 months ago - Pushed at: about 3 years ago - Stars: 135 - Forks: 136
SinaKarvandi/hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
Language: VHDL - Size: 46.9 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 2
ShonTaware/SRAM_SKY130
Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
Language: SourcePawn - Size: 20.2 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 23 - Forks: 7
