spcl/dace

DaCe - Data Centric Parallel Programming

Language: Python - Size: 50.2 MB - Last synced: 3 days ago - Pushed: 4 days ago - Stars: 468 - Forks: 116

Prajjv/RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

Language: Tcl - Size: 146 KB - Last synced: 4 days ago - Pushed: over 1 year ago - Stars: 4 - Forks: 1

Koushik2824/HLS-For-Digit-Recognition Fork of Siddardha824/vlsiModel

Course Project for CS577, Using keras2c to make machine learning model vivado synthesizable

Size: 50.1 MB - Last synced: 11 days ago - Pushed: 11 days ago - Stars: 0 - Forks: 0

jmduarte/HLS_hls4ml_Tutorial

HLS & hls4ml Tutorial

Language: Jupyter Notebook - Size: 16.9 MB - Last synced: 9 days ago - Pushed: almost 4 years ago - Stars: 5 - Forks: 3

spcl/gemm_hls

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

Language: C++ - Size: 16.7 MB - Last synced: 23 days ago - Pushed: about 2 years ago - Stars: 282 - Forks: 49

spcl/hls_tutorial_examples

Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

Language: C++ - Size: 1.27 MB - Last synced: 23 days ago - Pushed: over 2 years ago - Stars: 180 - Forks: 39

definelicht/hlslib

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

Language: C++ - Size: 577 KB - Last synced: 28 days ago - Pushed: 28 days ago - Stars: 287 - Forks: 52

benjmarshall/hlsclt

A Vivado HLS Command Line Helper Tool

Language: Python - Size: 62.5 KB - Last synced: 16 days ago - Pushed: over 2 years ago - Stars: 36 - Forks: 11

fastmachinelearning/hls4ml

Machine learning on FPGAs using HLS

Language: C++ - Size: 251 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 1,086 - Forks: 379

zslwyuan/Hi-ClockFlow

Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis

Size: 7.81 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 1 - Forks: 0

spcl/apfp

FPGA acceleration of arbitrary precision floating point computations.

Language: C++ - Size: 304 KB - Last synced: 23 days ago - Pushed: about 2 years ago - Stars: 32 - Forks: 4

spcl/nbody_hls

Implementation of the N^2-formulation of N-body simulation with Vivado HLS for SDAccel platforms.

Language: C++ - Size: 4.96 MB - Last synced: 23 days ago - Pushed: about 2 months ago - Stars: 8 - Forks: 4

yangjl-cs/stereo-vision-fpga

Real-time binocular stereo vision FPGA system with OV5640 cameras

Language: Tcl - Size: 23.9 MB - Last synced: about 1 month ago - Pushed: almost 2 years ago - Stars: 57 - Forks: 20

HawkPhantom/rgb2grayscale

A HLS IP to convert 24 bit RGB data to Grayscale data on AXI interface

Language: C++ - Size: 13.4 MB - Last synced: 2 months ago - Pushed: almost 4 years ago - Stars: 1 - Forks: 1

UCLA-VAST/AutoBridge

[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

Language: C++ - Size: 11.1 MB - Last synced: 3 months ago - Pushed: over 1 year ago - Stars: 113 - Forks: 24

n-roussos/A-framework-for-developing-Neural-Networks-in-hardware-accelerators Fork of georgevangelou/A-framework-for-developing-Neural-Networks-in-hardware-accelerators

This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.

Language: C - Size: 25 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 2 - Forks: 0

Licheng-Guo/vivado-hls-broadcast-optimization

[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

Language: Ada - Size: 10.8 MB - Last synced: about 1 month ago - Pushed: over 3 years ago - Stars: 32 - Forks: 8

benjmarshall/go-hlsclt

A rewrite of the hlsclt tool in Go!

Size: 1000 Bytes - Last synced: 5 months ago - Pushed: almost 7 years ago - Stars: 1 - Forks: 0

ngiambla/qvmi

Quick Verilog Module Isolator - Isolates a design for testing.

Language: Verilog - Size: 233 KB - Last synced: 5 months ago - Pushed: over 5 years ago - Stars: 3 - Forks: 0

georgevangelou/A-framework-for-developing-Neural-Networks-in-hardware-accelerators

This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.

Language: C - Size: 25 MB - Last synced: 4 months ago - Pushed: about 2 years ago - Stars: 7 - Forks: 1

zhutmost/stereo-vision-fpga

Real-time binocular stereo vision FPGA system with OV5640 cameras

Language: Tcl - Size: 1.53 MB - Last synced: 23 days ago - Pushed: almost 5 years ago - Stars: 24 - Forks: 4

lastweek/fpga_readings

Recipe for FPGA cooking

Language: Verilog - Size: 51.8 MB - Last synced: 7 months ago - Pushed: almost 3 years ago - Stars: 258 - Forks: 56

Duvindu/pynq

Language: Tcl - Size: 486 KB - Last synced: 7 months ago - Pushed: about 6 years ago - Stars: 2 - Forks: 0

delhatch/Mandel_HLS

Using Vivado HLS to create floating point IP, used to accelerate a Zynq system. Multiple engines are instantiated.

Language: VHDL - Size: 36.4 MB - Last synced: 7 months ago - Pushed: over 6 years ago - Stars: 1 - Forks: 4

junwha0511/MNIST-FPGA-Accelarator

MNIST accelerator using pynq-z2 and the binary qunatization

Language: C++ - Size: 13.4 MB - Last synced: 6 months ago - Pushed: over 1 year ago - Stars: 9 - Forks: 1

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Language: VHDL - Size: 46.9 KB - Last synced: 7 months ago - Pushed: 8 months ago - Stars: 2 - Forks: 1

Arjun-Narula/Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

Language: JavaScript - Size: 2.07 MB - Last synced: 8 months ago - Pushed: almost 4 years ago - Stars: 29 - Forks: 7

spcl/stencil_hls

Implementation of time and space-tiled stencil in Vivado HLS.

Language: C++ - Size: 225 KB - Last synced: 23 days ago - Pushed: over 3 years ago - Stars: 7 - Forks: 5

linkingmon/MSOC2020

Multimedia SoC design (2020 Fall)

Language: C - Size: 16 MB - Last synced: 10 months ago - Pushed: over 3 years ago - Stars: 3 - Forks: 0

frblazquez/ACA

Advanced Computer Architecture at EPFL.

Language: VHDL - Size: 18.6 MB - Last synced: 10 months ago - Pushed: over 2 years ago - Stars: 3 - Forks: 1

FloyedShen/mnist_hls

Lenet for MNIST handwritten digit recognition using Vivado hls tool

Language: Objective-C - Size: 2.5 MB - Last synced: 7 months ago - Pushed: almost 4 years ago - Stars: 31 - Forks: 10

prateekshyap/VLSI-Project

Language: C++ - Size: 23.3 MB - Last synced: 10 months ago - Pushed: about 2 years ago - Stars: 0 - Forks: 0

CSpyridakis/Reconfigurable-Computing 📦

Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)

Language: C++ - Size: 114 MB - Last synced: 10 months ago - Pushed: over 3 years ago - Stars: 3 - Forks: 2

get-ipipe/ipipe

Python-based Xilinx Vivado IP Integrator (IPI) pipeline supporting HLS and RTL blocks.

Language: VHDL - Size: 797 KB - Last synced: 12 months ago - Pushed: 12 months ago - Stars: 2 - Forks: 0

vishalcseiitg/CS-577-C-BASED-VLSI-DESIGN

Course taken by Dr Chandan Karfa of Dept. of CSE, IIT Guwahati.

Language: C++ - Size: 71.2 MB - Last synced: 12 months ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

AnoushkaVyas/FPGA

Google Page Rank Algorithm on FPGA

Language: Verilog - Size: 153 KB - Last synced: 12 months ago - Pushed: over 3 years ago - Stars: 0 - Forks: 0

jiangwx/SkrSkr

The second place winner for DAC-SDC 2020

Language: Tcl - Size: 70.7 MB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 89 - Forks: 24

Manwlis/FPGA-accelerated-Hadamard-products-with-threshold 📦

Reconfigurable Digital Systems HRY591-project.

Language: C - Size: 197 MB - Last synced: 11 months ago - Pushed: over 1 year ago - Stars: 1 - Forks: 1

medalotte/HLS-canny-edge-detection

FPGA implementation of Canny edge detection by using Vivado HLS

Language: C++ - Size: 1.2 MB - Last synced: about 1 year ago - Pushed: almost 5 years ago - Stars: 40 - Forks: 12

ChienKaiMa/2021_ACA_HLS_team05

High level synthesis projects and practices

Language: C++ - Size: 54.7 KB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 3 - Forks: 0

miltosmac/TCAD

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs

Language: C++ - Size: 246 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0

lirui-shanghaitech/A-convolution-kernel-implemented-by-Vivado-HLS

This project implements a convolution kernel based on vivado HLS on zcu104

Language: C++ - Size: 9.12 MB - Last synced: about 1 year ago - Pushed: about 4 years ago - Stars: 23 - Forks: 7

duartegalvao/ArduZynq-Tutorials

Simple tutorials for getting started with programming on Trenz ArduZynq boards.

Size: 1.3 MB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 5 - Forks: 0

JoshuaEbenezer/vivado_hls

Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted to RTL using Vivado HLS or SDSoC.

Language: C++ - Size: 66.4 KB - Last synced: about 1 year ago - Pushed: about 5 years ago - Stars: 9 - Forks: 5

Kenta11/vivado_hls_create_project

generate Makefile and tcl script

Language: Python - Size: 38.1 KB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 3 - Forks: 0

mavalderrama/AI-flood-prediction-system

This is an IoT Edge computing system powered by an ANN to predict floods on cities near Mississippi river

Language: Objective-C - Size: 37.7 MB - Last synced: about 1 year ago - Pushed: about 4 years ago - Stars: 1 - Forks: 0

albertopirillo/logical-networks-project-2020

Implementation in VHDL of an HW component capable of recalibrating the constrast of an image stored in an external memory, using an histogram equalization algorithm.

Language: VHDL - Size: 3.1 MB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 0 - Forks: 0

sopynq/huffman-encoding-core

Huffman encoding core (Vivado HLS)

Language: Tcl - Size: 588 KB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 9 - Forks: 5

lorenzoferretti/db4hls

Repository of DB4HLS. A database of design space exploration in high-level synthesis.

Language: Python - Size: 76.2 KB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 1 - Forks: 0

tharaka27/ImageStitcherFAST

CPU implementation of the Image stitching using FAST. For FPGA implementation visit tharaka27-SocStitcher.

Language: C++ - Size: 21.9 MB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 9 - Forks: 5

wubinary/two_stream_soc

SOC of two_stream action recognition on ZCU102

Language: Jupyter Notebook - Size: 35.7 MB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 6 - Forks: 1

Sanjay-A-Menon/FES256

A fast and efficient implementation of a SHA256 cracker

Language: VHDL - Size: 156 MB - Last synced: about 1 year ago - Pushed: about 4 years ago - Stars: 3 - Forks: 1

fred-framework/dart_ips

a library of DART-enabled hw IPs

Language: C - Size: 2.66 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 2 - Forks: 1

VenciFreeman/LeNet

A simple DNN for handwritten numbers recognition. Written in C++, and optimized using Vivado HLS.

Language: C++ - Size: 215 KB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 1 - Forks: 0

JochiSt/AI_FPGA

running ANN on an FPGA

Language: SystemVerilog - Size: 313 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

brnaguiar/cr-16bit-lfsr

Implementation of a (soft) coprocessor for the computation of a 16 bit LFSR.

Language: VHDL - Size: 43.8 MB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 0 - Forks: 1

z1skgr/reconf-Computing__HLS

High Level synthesis of data transfer in Vivado, Vivado HLS

Language: C++ - Size: 53.2 MB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 0 - Forks: 0

diamantopoulos/diamantopoulos.github.io

Dionysios Diamantopoulos Web Edition

Language: JavaScript - Size: 10.5 MB - Last synced: 11 months ago - Pushed: almost 3 years ago - Stars: 0 - Forks: 0

bashidagha/QPSK-VivadoHLS Fork of ttown523/QPSK-VivadoHLS

QPSK system implemented using Vivado HLS

Language: C++ - Size: 3.23 MB - Last synced: about 1 year ago - Pushed: about 9 years ago - Stars: 3 - Forks: 0

AbdullahAshfaq/Local-Thresh-xilinxHLS

Designing local adaptive thresholding using integral images from scratch. "Efficient Implementation of Local Adaptive Thresholding Techniques Using Integral Images" by Faisal Shafait, Daniel Keysers, Thomas M. Breuel was used as guideline.

Language: C++ - Size: 5.86 KB - Last synced: 12 months ago - Pushed: almost 6 years ago - Stars: 2 - Forks: 0