Amalkrishnan-P/FPGA_Based_Fault_Analyser_for_Industrial_Motors

Simple hardware accelerator for fft computation

Language: Jupyter Notebook - Size: 2.93 MB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 0 - Forks: 0

m-spr/RCEHDC

An automated HDC platform

Language: VHDL - Size: 16.2 MB - Last synced at: 28 days ago - Pushed at: 28 days ago - Stars: 9 - Forks: 5

andre1araujo/YOLO-on-PYNQ-Z2

This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step-by-step tutorial associated so everyone can do it.

Language: C++ - Size: 173 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 45 - Forks: 9

junwha/MNIST-FPGA-Accelarator

MNIST accelerator using binary qunatization on Xilinx pynq-z2

Language: C++ - Size: 13.4 MB - Last synced at: 2 months ago - Pushed at: 8 months ago - Stars: 12 - Forks: 2

PCov3r/FPGA_Handwritten_digit_recognition

A Verilog implementation of a hand-written digit recognition Neural Network

Language: Jupyter Notebook - Size: 2.91 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 5 - Forks: 2

saulcarvalho/ClassProj-CE-Modulators-Proj

2023. FSK and PSK modulators done in PYNQ-Z2 board for the class of Configurable Electronics.

Language: Python - Size: 1.93 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

max2ma/LSTM_HLS

Language: C++ - Size: 1 MB - Last synced at: 6 months ago - Pushed at: about 6 years ago - Stars: 4 - Forks: 0

Logicademy/PYNQ-SoC-Builder

This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.

Language: Python - Size: 23.4 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 2

riyasach189/Vitis_HLS_2022.1_Examples

This is a collection of some examples designed in the Vivado Design Suite.

Language: Tcl - Size: 1.18 MB - Last synced at: 2 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

rishz09/digital-safe-verilog

A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board

Language: Tcl - Size: 2.06 MB - Last synced at: 2 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

Prithvish04/reconfigurable_project

Canny edge detection in HLS

Language: Jupyter Notebook - Size: 10.1 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 2 - Forks: 0

mariodruiz/PYNQ_tutorials

PYNQ Tutorials

Language: Jupyter Notebook - Size: 10.7 KB - Last synced at: 10 days ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

franout/Cogitantium

Hardware Accelerator for ML

Language: VHDL - Size: 2.51 GB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

cpantel/TheZynqBook

Exercises from the book

Language: VHDL - Size: 60.7 MB - Last synced at: 12 months ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

ZeroX29a/PynqZ2

Complete collection of general resource of Pynq Z2

Language: Tcl - Size: 67 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

dsa-shua/FPGA-SystolicArray

Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

Language: SystemVerilog - Size: 1.59 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

sefaburakokcu/quantized-yolov5

Low Precision(quantized) Yolov5

Language: Python - Size: 9.38 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 24 - Forks: 5

huseyindas/pynq-z2-deepface-caffessd-tester

It is a testing tool for DeepFace and Caffe SSD models. This tool can be used for face recognition and object detection. This tool has been developed to be compatible with the Pynq Z2 embedded card.

Language: Python - Size: 11.7 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

abidanBrito/fpga-polymul

Polynomial multiplier for the Xilinx Pynq-z2 FPGA board.

Language: VHDL - Size: 80.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

XAli-SHX/FPGA-Implementation-of-Image-Processing-for-MNIST-Dataset-Based-on-CNN-Algorithm

FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)

Language: VHDL - Size: 64.9 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 0

sefaburakokcu/finn-quantized-yolo

Low-Precision YOLO on PYNQ with FINN

Language: Jupyter Notebook - Size: 11.4 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 18 - Forks: 3

PoliTo-ASAC-Lab/ASAC_CPM

ASC_CPM is a Cluster Power Manager solution, to be used for testing purposes or extensive fault injection campaigns involving a cluster of devices. (Daniele Rizzieri - 2023)

Language: Python - Size: 34.9 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

PoliTo-ASAC-Lab/PYNQ_UARTopus

Python platform to use a TUL PYNQ-Z2 development board to virtualize up to 12 UART connections (tx+rx@9600bps) over TCP-IP

Language: Python - Size: 44.4 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

ChienKaiMa/2021_ACA_HLS_team05

High level synthesis projects and practices

Language: C++ - Size: 54.7 KB - Last synced at: 6 days ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

gubbriaco/FPGA-VHDL-filtering-circuit-grayscale-images

A project that involves the hardware design (VHDL) of a circuit on FPGA that performs the filtering of an image through an isotropic filter. The circuit is also tested and validated (both from the point of view of the error and from the point of view of the quality of the filtering) through procedures described in MATLAB.

Language: C - Size: 76.8 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

cteqeu/PynqZ2

Size: 1.95 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

axelvanherle/IoTProject_1 📦

By Sem Kirkels, Nathan Bruggeman, Indy Penders and Axel Vanherle. This sends a random value from the pynq to a server running openremote.

Language: C - Size: 119 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 2

MakarenaLabs/Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow

Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.

Language: Jupyter Notebook - Size: 167 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 20 - Forks: 4

xupsh/pynq-supported-board-file

Size: 779 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 15 - Forks: 6

kuoyaoming93/sem-ip_pynq

SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2

Language: Tcl - Size: 17.8 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 5 - Forks: 1

elenamarreroo/Proyecto-IoT

Proyecto que utiliza sensores de Grove para medir la temperatura, el nivel de humedad y la luminosidad y crear así un invernadero monitorizado para controlar que las plantas tengan las mejores condiciones para vivir.

Language: Jupyter Notebook - Size: 1.42 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

franout/tensorflow_for_pynqz2

tensorflor 2.1 wheel for pynq z2 ( zynq 7000 xilinx SoC ), cross compiled with different compiler's flags using the script provided by tensorflow for building it for rasberry

Language: Shell - Size: 11.7 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 4 - Forks: 0

berniGelectronic/FPGA_Multimedia_Player

MSc Final Project

Language: C - Size: 2.68 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 2

Sanjay-A-Menon/FES256

A fast and efficient implementation of a SHA256 cracker

Language: VHDL - Size: 156 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 3 - Forks: 1

gkogkalatze/A-PYNQ-Theremin

Creating a Theremin instrument inside the PYNQ-Z2 using a Grove ultrasonic ranger. Done by: Konstantinos Gkogkalatze, Yiannis Michael, Michail Kasmeridis

Language: Jupyter Notebook - Size: 2.61 MB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

Gabriele-bot/PYNQ_IA

Repository that contains some neural network inferences on PYNQ-Z2 board employing hls4ml

Language: Ada - Size: 233 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1

Gabriele-bot/FPGA_projects

Some of my projects/mistakes on various FPGA boards

Language: VHDL - Size: 725 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

maximyudayev/PYNQ-Z2-Morse-Code-Lock

VHDL Morse Code Lock for PYNQ-Z2 board for the final lab assignment of the Bachelor of Electronics and ICT course of Digital Systems at KU Leuven 2019-2020

Language: HTML - Size: 2.39 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

reed-foster/pynq-audio

RTL and python for using the ADAU1761 audio codec on the Pynq-Z2 board from TUL

Language: SystemVerilog - Size: 4.24 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 1

omerferhatt/pynq-tflite-runtime

PYNQ Z2 Prebuilt binaries and wheels

Size: 9.58 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

kuoyaoming93/axi_uartlite_pynq Fork of parthpower/axi_uartlite_pynq

PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx

Language: Tcl - Size: 15.9 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0

Sumegh-git/Xilinx-Innovation-Challenge

Team reverse_biased

Language: Python - Size: 15.1 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 1