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GitHub topics: alveo

Xilinx/Vitis-Tutorials

Vitis In-Depth Tutorials

Language: C - Size: 779 MB - Last synced at: 5 days ago - Pushed at: 12 days ago - Stars: 1,386 - Forks: 568

Xilinx/Vitis_Accel_Examples

Vitis_Accel_Examples

Language: Makefile - Size: 107 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 538 - Forks: 217

Xilinx/ResNet50-PYNQ 📦

Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ

Language: C++ - Size: 8.5 MB - Last synced at: 9 days ago - Pushed at: over 3 years ago - Stars: 58 - Forks: 15

Xilinx/finn-examples

Dataflow QNN inference accelerator examples on FPGAs

Language: Python - Size: 23.5 MB - Last synced at: about 1 month ago - Pushed at: 2 months ago - Stars: 212 - Forks: 62

ECASLab/cynq

PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.

Language: C++ - Size: 4.55 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 24 - Forks: 4

Xilinx/xup_vitis_network_example

VNx: Vitis Network Examples

Language: Jupyter Notebook - Size: 2.35 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 131 - Forks: 42

Xilinx/5point-PYNQ

5-point Relative Pose Problem for PYNQ

Language: C - Size: 293 KB - Last synced at: 9 days ago - Pushed at: about 5 years ago - Stars: 6 - Forks: 2

Xilinx/Alveo-PYNQ

Introductory examples for using PYNQ with Alveo

Language: Jupyter Notebook - Size: 1.16 MB - Last synced at: 10 months ago - Pushed at: about 2 years ago - Stars: 47 - Forks: 17

DYGV/FPGA-Based-EdgeAI-Prototypes

Xilinx DPU(Vitis AI)を用いたエッジAI実現に向けたサンプルプログラム

Language: C++ - Size: 31.6 MB - Last synced at: 3 days ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

andrea-zanette/HippoScan

A framework to train a ResUNet architecture, quantize, compile and execute it on an FPGA.

Language: Jupyter Notebook - Size: 90.8 KB - Last synced at: 8 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

MakarenaLabs/Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow

Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.

Language: Jupyter Notebook - Size: 167 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 20 - Forks: 4

Gabriele-bot/ALVEO-PYNQ_ML

Neural network inferences on Alveo cards with hls4ml framework

Language: Ada - Size: 786 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 1

Accelize/nimbix_drm_demo 📦

This demo is intended to demonstrate the FPGA design protection and metering capability provided by the Accelize Distribution Platform.

Language: C++ - Size: 28.6 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0

fpgasystems/erbium

Business Rule Engine Hardware Accelerator

Language: VHDL - Size: 1.08 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 12 - Forks: 3

Alveo/alveo-transcriber

Web application to transcribe data for the Alveo project

Language: TypeScript - Size: 5.41 MB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 1

nixir/callAlveoFromMATLAB

This Repo contains a programs of calling Xilinx Alveo accelerator card from MATLAB

Language: C - Size: 10.3 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0