Samuelbec025/Verilog-Matrix-Multiplier

This is a simple project that shows how to multiply two 8x8 matrixes in Verilog.

Language: Verilog - Size: 75.2 KB - Last synced: about 2 hours ago - Pushed: about 2 hours ago - Stars: 0 - Forks: 0

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1000 KB - Last synced: about 12 hours ago - Pushed: about 12 hours ago - Stars: 596 - Forks: 180

pConst/basic_verilog

Must-have verilog systemverilog modules

Language: Verilog - Size: 54.2 MB - Last synced: about 10 hours ago - Pushed: 1 day ago - Stars: 1,447 - Forks: 336

efetunca/Zynq-7000-TFTP-Server

A TFTP server running on Zynq-7000

Language: C - Size: 3.83 MB - Last synced: about 17 hours ago - Pushed: 2 days ago - Stars: 0 - Forks: 0

tsfpga/tsfpga

A flexible and scalable development platform for modern FPGA projects.

Language: Python - Size: 2.17 MB - Last synced: 2 days ago - Pushed: 3 days ago - Stars: 7 - Forks: 1

Xilinx/brevitas

Brevitas: neural network quantization in PyTorch

Language: Python - Size: 19.5 MB - Last synced: 2 days ago - Pushed: 3 days ago - Stars: 1,097 - Forks: 175

shrine-maiden-heavy-industries/torii-boards Fork of amaranth-lang/amaranth-boards

Torii HDL Board Definitions

Language: Python - Size: 45 MB - Last synced: 5 days ago - Pushed: 5 days ago - Stars: 0 - Forks: 0

t-kuha/kv260

Xilinx Kria KV260 Vision AI Starter Kit

Language: C - Size: 1.07 MB - Last synced: 5 days ago - Pushed: 5 days ago - Stars: 0 - Forks: 1

f4pga/prjxray

Documenting the Xilinx 7-series bit-stream format.

Language: Python - Size: 6.4 MB - Last synced: 6 days ago - Pushed: 6 days ago - Stars: 739 - Forks: 148

ECASLab/cynq

PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.

Language: C++ - Size: 2.79 MB - Last synced: 3 days ago - Pushed: 3 days ago - Stars: 15 - Forks: 1

f32c/f32c

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

Language: C - Size: 11.2 MB - Last synced: 7 days ago - Pushed: 7 days ago - Stars: 395 - Forks: 110

menotti/RemoteMicrocontrollerLab Fork of rafaelaroca/RemoteMicrocontrollerLab

A set of PHP files, scripts and database to allow remote users to edit programs, upload code and access the serial port of real microcontrollers.

Language: PHP - Size: 5.9 MB - Last synced: 7 days ago - Pushed: 7 days ago - Stars: 1 - Forks: 0

kdg-auts/ALINX-AX309

Laboratory workshop for ALINX AX309 development board (with FPGA Spartan 6)

Language: VHDL - Size: 3.36 MB - Last synced: 7 days ago - Pushed: 8 days ago - Stars: 9 - Forks: 5

jeremiah-c-leary/eda-log-file-warning-suppressor

Suppresses warnings in EDA logfiles.

Language: Python - Size: 202 KB - Last synced: 9 days ago - Pushed: 10 days ago - Stars: 2 - Forks: 1

auperatech/VMSS2.0

Public Repo for VMSS2.0

Language: C - Size: 72.3 MB - Last synced: 9 days ago - Pushed: 9 days ago - Stars: 11 - Forks: 1

HDLGen-ChatGPT/PYNQ-SoC-Builder

This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.

Language: Python - Size: 18.6 MB - Last synced: 8 days ago - Pushed: 9 days ago - Stars: 1 - Forks: 1

open-sdr/openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Language: C - Size: 23.5 MB - Last synced: 8 days ago - Pushed: about 1 month ago - Stars: 3,577 - Forks: 606

MJoergen/HyperRAM

Portable HyperRAM controller

Language: VHDL - Size: 3.31 MB - Last synced: 10 days ago - Pushed: 11 days ago - Stars: 44 - Forks: 8

Shuregg/FPGA-practicum

learning about FPGA

Language: Tcl - Size: 1.24 MB - Last synced: 11 days ago - Pushed: 11 days ago - Stars: 0 - Forks: 0

eugene-tarassov/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Language: Tcl - Size: 35.4 MB - Last synced: 11 days ago - Pushed: 11 days ago - Stars: 741 - Forks: 173

Xilinx/RapidWright

Build Customized FPGA Implementations for Vivado

Language: Java - Size: 7.07 MB - Last synced: 13 days ago - Pushed: 14 days ago - Stars: 271 - Forks: 101

stnolting/neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Language: VHDL - Size: 644 KB - Last synced: 16 days ago - Pushed: 19 days ago - Stars: 52 - Forks: 15

AlvaroDavi5/Programacao_e_Desenvolvimento

Language: JavaScript - Size: 306 MB - Last synced: 15 days ago - Pushed: 16 days ago - Stars: 0 - Forks: 0

ultraembedded/biriscv

32-bit Superscalar RISC-V CPU

Language: Verilog - Size: 2.98 MB - Last synced: 16 days ago - Pushed: over 2 years ago - Stars: 771 - Forks: 134

jmduarte/HLS_hls4ml_Tutorial

HLS & hls4ml Tutorial

Language: Jupyter Notebook - Size: 16.9 MB - Last synced: 6 days ago - Pushed: almost 4 years ago - Stars: 5 - Forks: 3

hdl-util/hdmi

Send video/audio over HDMI on an FPGA

Language: SystemVerilog - Size: 4.13 MB - Last synced: 16 days ago - Pushed: 3 months ago - Stars: 1,011 - Forks: 105

iDoka/awesome-fpga-boards

:atm: Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................

Size: 9.28 MB - Last synced: 5 days ago - Pushed: over 3 years ago - Stars: 84 - Forks: 11

pkill37/asic-linreg

ASIC for executing vectorized gradient descent on linear regression problems.

Language: VHDL - Size: 110 MB - Last synced: 19 days ago - Pushed: almost 6 years ago - Stars: 2 - Forks: 1

gau-nernst/macaque-detection

Detect macaques with Xilinx KV260! Powered by CenterNet

Language: Python - Size: 82 KB - Last synced: 20 days ago - Pushed: about 2 years ago - Stars: 0 - Forks: 0

Xilinx/xup_vitis_network_example

VNx: Vitis Network Examples

Language: Jupyter Notebook - Size: 2.34 MB - Last synced: 20 days ago - Pushed: 20 days ago - Stars: 124 - Forks: 41

princeranjan03/ImageEncryption_I-CHIP

This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.

Language: Verilog - Size: 7.3 MB - Last synced: 20 days ago - Pushed: 20 days ago - Stars: 0 - Forks: 0

jurihock/visualapplets.py

Python bindings for Basler's VisualApplets TCL script generation.

Language: Python - Size: 146 KB - Last synced: 20 days ago - Pushed: over 2 years ago - Stars: 3 - Forks: 0

definelicht/hlslib

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

Language: C++ - Size: 577 KB - Last synced: 24 days ago - Pushed: 25 days ago - Stars: 287 - Forks: 52

Parretto/DisplayPort

DisplayPort IP-core

Language: Verilog - Size: 2.37 MB - Last synced: 24 days ago - Pushed: 24 days ago - Stars: 32 - Forks: 2

fpgasystems/Vitis_with_100Gbps_TCP-IP

100 Gbps TCP/IP stack for Vitis shells

Language: C++ - Size: 2.17 MB - Last synced: 24 days ago - Pushed: 24 days ago - Stars: 160 - Forks: 68

open-sdr/openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Language: Verilog - Size: 484 MB - Last synced: 24 days ago - Pushed: 5 months ago - Stars: 621 - Forks: 215

trabucayre/openFPGALoader

Universal utility for programming FPGA

Language: C++ - Size: 5.6 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 1,023 - Forks: 222

halfmanhalftaco/fpga-docker

Tools for running FPGA vendor toolchains with Docker

Language: Makefile - Size: 32.2 KB - Last synced: 12 days ago - Pushed: about 1 year ago - Stars: 66 - Forks: 14

leonow32/verilog-fpga

Many peripherals in Verilog ready to use

Language: Verilog - Size: 4.89 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 22 - Forks: 3

Xilinx/ResNet50-PYNQ 📦

Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ

Language: C++ - Size: 8.5 MB - Last synced: 19 days ago - Pushed: over 2 years ago - Stars: 50 - Forks: 15

liuwei9/SpinalHDL_CNN_Accelerator

CNN accelerator implemented with Spinal HDL

Language: Scala - Size: 2.18 MB - Last synced: about 1 month ago - Pushed: over 2 years ago - Stars: 17 - Forks: 2

stv0g/xilinx-hw-server-docker

Run a Xilinx hw_server in a Docker container

Language: Dockerfile - Size: 449 KB - Last synced: 16 days ago - Pushed: 12 months ago - Stars: 15 - Forks: 5

triqadafi/Triqadafi_FrequencyCounter

Handcrafted high resolution multichannel frequency counter 😉

Language: C++ - Size: 1010 KB - Last synced: about 1 month ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0

hedhyw/simple-4bit-cpu

Vivado project with example of simple 4bit CPU

Language: Verilog - Size: 671 KB - Last synced: about 1 month ago - Pushed: about 5 years ago - Stars: 2 - Forks: 0

qubeck78/tangerineSOCMA7

tangyRiscVSOC - Mimas A7 port

Language: VHDL - Size: 25 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

AranelLindi/AXI_SpaceWire_IP

Standalone IP with ARM-AMBA/AXI capable device. Enables sending and receiving data via SpaceWire protocol. Tested on Xilinx FPGA (ZYNQ).

Language: VHDL - Size: 59.8 MB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 1 - Forks: 0

subhadeeproy3902/PCC-CS492

This repository contains all the VHDL codes I practised as a part of the Computer Architecture Lab in the 4th semester of my B.Tech CSE curriculum.

Language: VHDL - Size: 16.8 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

siidheesh/EE2020

EE2020 AY16/17 Design Project: FPGA-based Digital Signal Generator

Language: VHDL - Size: 62.2 MB - Last synced: about 1 month ago - Pushed: about 7 years ago - Stars: 3 - Forks: 0

hdl-modules/hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Language: VHDL - Size: 1.82 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 36 - Forks: 1

fischermoseley/manta

A configurable and approachable tool for FPGA debugging and rapid prototyping.

Language: Python - Size: 9.59 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 41 - Forks: 4

FlatAssembler/PicoBlaze_Simulator_in_JS

Simulator (more accurately: an assembler and an emulator) for Xilinx PicoBlaze, runnable in a browser.

Language: JavaScript - Size: 30.2 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 22 - Forks: 3

MeowLucian/SDR_FM_Radio

:radio: Using Software Designed Radio to transmit & receive FM signal

Language: Matlab - Size: 16.8 MB - Last synced: 12 days ago - Pushed: about 6 years ago - Stars: 34 - Forks: 19

j-schacht/xilinx_zcu102_trustzone_demo

Tutorial and base project: TEE on AMD Zynq UltraScale+ using Arm TrustZone

Language: C - Size: 69 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

coldnew/zybo-templates

Basic project template for Xilinx zynq-7000 ZYBO board

Language: C - Size: 3.02 MB - Last synced: about 1 month ago - Pushed: about 6 years ago - Stars: 1 - Forks: 2

JuantAldea/vitis_docker Fork of delafthi/vivado2022.1_docker

Docker container containing the Vitis 2023.2 tools & PetaLinux

Language: Dockerfile - Size: 3.33 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

BrianHGinc/BrianHG-DDR3-Controller

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

Language: SystemVerilog - Size: 9.94 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 64 - Forks: 28

MasterPlayer/mpf_xpm_fifo_cmd_sync

xpm macros wrapper of fifo with fwft for instantiate in other projects as module

Language: SystemVerilog - Size: 6.84 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

FlorianFrank/verilog-baremetal-sram-controller

A bare-metal SRAM memory controller suitable for Xilinx FPGAs.

Language: Verilog - Size: 775 KB - Last synced: 16 days ago - Pushed: 4 months ago - Stars: 2 - Forks: 0

spcl/apfp

FPGA acceleration of arbitrary precision floating point computations.

Language: C++ - Size: 304 KB - Last synced: 20 days ago - Pushed: about 2 years ago - Stars: 32 - Forks: 4

HDLGen-ChatGPT/HDLGen-ChatGPT

HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

Language: Python - Size: 125 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 11 - Forks: 9

pbannister/dma_ip_drivers Fork of Xilinx/dma_ip_drivers

Fork of Xilinx QDMA IP Drivers to stage changes to upstream.

Language: C - Size: 19.7 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

Xilinx/Alveo-PYNQ

Introductory examples for using PYNQ with Alveo

Language: Jupyter Notebook - Size: 1.16 MB - Last synced: about 1 month ago - Pushed: about 1 year ago - Stars: 47 - Forks: 16

AranelLindi/SpaceWireRouter

Fully functional SpaceWire router. Implemented in VHDL and continuously developed. See manual. Repository contains also an UART-SpaceWire adapter and several implementation files including constraints for Xilinx FPGAs.

Language: VHDL - Size: 36.7 MB - Last synced: 14 days ago - Pushed: 14 days ago - Stars: 5 - Forks: 0

LeiWang1999/FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Size: 58.6 KB - Last synced: about 2 months ago - Pushed: about 2 years ago - Stars: 3,249 - Forks: 593

ArioKian/Xilinx_Zynq7000_PS_SLCR_RegistersDrivers

Zynq-7000 PS side drivers for SLCR Registers.

Language: C - Size: 6.84 KB - Last synced: about 2 months ago - Pushed: 2 months ago - Stars: 0 - Forks: 0

lvgl/lv_port_xilinx_zedboard_vitis

This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals

Language: C - Size: 82 MB - Last synced: 16 days ago - Pushed: 7 months ago - Stars: 14 - Forks: 4

khalie/alarm_clock

Logisim and VHDL Files for an alarm_clock that was realized on a development board at University

Language: VHDL - Size: 570 KB - Last synced: about 2 months ago - Pushed: about 7 years ago - Stars: 3 - Forks: 0

kekyo/Spartan2Bone

The prototyping board for Xilinx Spartan-II FPGA processor.

Language: Eagle - Size: 81.2 MB - Last synced: 16 days ago - Pushed: about 7 years ago - Stars: 6 - Forks: 0

EMATech/zynq_book_pynq-z1

Zynq Book Tutorials adapted for the Digilent PYNQ-Z1

Language: Tcl - Size: 6.84 KB - Last synced: about 2 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

trivialmips/nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

Language: SystemVerilog - Size: 20.4 MB - Last synced: about 1 month ago - Pushed: almost 4 years ago - Stars: 553 - Forks: 95

f4pga/prjuray

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

Language: SystemVerilog - Size: 1.37 MB - Last synced: about 1 month ago - Pushed: over 2 years ago - Stars: 66 - Forks: 12

pavel-demin/red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

Language: Tcl - Size: 10.9 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 309 - Forks: 196

sahmad98/HardwareDesigns

Few of my VHDL hardware design for Xilinx Spartan 6 board

Language: VHDL - Size: 10.7 KB - Last synced: about 2 months ago - Pushed: almost 6 years ago - Stars: 1 - Forks: 0

vacagonzalo/soc-workflow-firmware

Example workflow project for firmware development in Vitis.

Language: C - Size: 318 KB - Last synced: 2 months ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

hpaluch/crnr-ii-intro

Introductory Verilog project for Digilent CoolRunner-II Starter Board featuring Xilinx XC2C256-7-TQ144 CPLD

Language: HTML - Size: 2.13 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 1 - Forks: 1

pronoym99/PN-Sequence-Generator

This is a simulation based VHDL code developed in Xilinx to demonstrate a 4-bit PN sequence generator.

Language: C++ - Size: 2.38 MB - Last synced: 2 months ago - Pushed: over 5 years ago - Stars: 2 - Forks: 0

VLSI-EDA/PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Language: VHDL - Size: 4.96 MB - Last synced: about 1 month ago - Pushed: over 3 years ago - Stars: 511 - Forks: 95

mandl/zamiacad

Language: Java - Size: 48.3 MB - Last synced: 2 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

themperek/cocotb-vivado

Limited python / cocotb interface to Xilinx Vivado XSIM simulator.

Language: Python - Size: 30.3 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 14 - Forks: 1

JeffDeCola/my-verilog-examples

A place to keep my synthesizable verilog examples.

Language: Verilog - Size: 13.1 MB - Last synced: 2 months ago - Pushed: 10 months ago - Stars: 27 - Forks: 9

chipsalliance/yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

Language: Verilog - Size: 4.57 MB - Last synced: about 1 month ago - Pushed: 4 months ago - Stars: 82 - Forks: 45

f4pga/prjxray-db

Project X-Ray Database: XC7 Series

Language: Shell - Size: 62.5 MB - Last synced: about 1 month ago - Pushed: over 2 years ago - Stars: 60 - Forks: 29

rice-systems/lofreq-fpga

FPGA Acceleration for the LoFreq variant caller

Language: C - Size: 20.5 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 5 - Forks: 0

tymonx/logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Language: SystemVerilog - Size: 820 KB - Last synced: about 2 months ago - Pushed: over 4 years ago - Stars: 248 - Forks: 53

tymonx/virtio

Virtio implementation in SystemVerilog

Language: SystemVerilog - Size: 44.9 KB - Last synced: about 2 months ago - Pushed: over 6 years ago - Stars: 44 - Forks: 9

ArioKian/Xilinx_Zynq7000_ZynqUltraScalePlus_PS_SdCardDrivers

Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.

Language: C - Size: 7.81 KB - Last synced: about 2 months ago - Pushed: 2 months ago - Stars: 0 - Forks: 0

whutddk/MK64F-platform

A PCB platform based on the architecture of Arm + FPGA

Language: HTML - Size: 229 MB - Last synced: 16 days ago - Pushed: about 5 years ago - Stars: 1 - Forks: 4

Xilinx/PYNQ_Composable_Pipeline

PYNQ Composabe Overlays

Language: Tcl - Size: 5.36 MB - Last synced: 2 months ago - Pushed: 3 months ago - Stars: 59 - Forks: 21

pavel-demin/usb104-a7-notes

Notes on the USB104 A7 development board

Language: Tcl - Size: 1.11 MB - Last synced: 2 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

Language: Batchfile - Size: 48.6 MB - Last synced: 3 months ago - Pushed: 8 months ago - Stars: 254 - Forks: 54

kartikeya443/labwork_LNMIIT

Compilation of my laboratory work based on topics like signal processing, digital communication, computer networks, etc. implemented using languages like MATLAB, VHDL and C++, compiled on MATLAB, Xilinx's Vivado and Omnet++, documented using LaTeX.

Language: SuperCollider - Size: 25.1 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

iDoka/GOST-28147-89

Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher

Language: Verilog - Size: 34.2 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 12 - Forks: 2

z4yx/vivado-docker Fork of BBN-Q/vivado-docker

Dockerfile with Vivado for CI

Language: Dockerfile - Size: 15.6 KB - Last synced: 3 months ago - Pushed: about 4 years ago - Stars: 27 - Forks: 9

Xilinx/SDAccel_Examples

SDAccel Examples

Language: C++ - Size: 366 MB - Last synced: 2 months ago - Pushed: almost 2 years ago - Stars: 348 - Forks: 210

ZipCPU/wb2axip

Bus bridges and other odds and ends

Language: Verilog - Size: 8.97 MB - Last synced: 3 months ago - Pushed: 4 months ago - Stars: 422 - Forks: 94

z4yx/petalinux-docker

Dockerfile to build docker images with Petalinux (Tested on version 2018.3~2021.1)

Language: Dockerfile - Size: 17.6 KB - Last synced: 3 months ago - Pushed: about 2 years ago - Stars: 110 - Forks: 63

suoto/hdl_checker

Repurposing existing HDL tools to help writing better code

Language: Python - Size: 1.05 MB - Last synced: 3 months ago - Pushed: 5 months ago - Stars: 179 - Forks: 20

pavel-demin/giga-zee-notes

Notes on the GigaZee modules

Language: C - Size: 289 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 4 - Forks: 0

19801201/SpinalHDL_CNN_Accelerator

CNN accelerator implemented with Spinal HDL

Language: Scala - Size: 2.25 MB - Last synced: 3 months ago - Pushed: 4 months ago - Stars: 113 - Forks: 31

UCLA-VAST/AutoBridge

[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

Language: C++ - Size: 11.1 MB - Last synced: 3 months ago - Pushed: over 1 year ago - Stars: 113 - Forks: 24