MEESAM749/Single-Cycle-Non-Pipelined-MIPS-32-Processor

This is a simulation of the MIPS32 Single Cycle Processor on Xilinx ISE written in Verilog.

Language: C - Size: 1.97 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

MEESAM749/RISC-V-PipelinedProcessor

RISC-V Pipelined Processor simulation in Verilog on Xilinx ISE

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yasnakateb/Threshold

🖼✏️ My first baby steps into the world of image processing

Language: Verilog - Size: 1.85 MB - Last synced at: about 2 months ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

Slatyo/SonarTracking

Small project to track things with a waterproof sonar sensor

Language: C++ - Size: 2.22 MB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

YehiaSharawy/MIPS-Architecture

Implementation of a MIPS processor architecture for a single cycle using VHDL

Language: C - Size: 748 KB - Last synced at: about 1 month ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

ashvnv/FPGA-Ping-Pong-game

Simple Ping Pong game on Xilinx Spartan 3E

Language: HTML - Size: 13.9 MB - Last synced at: about 2 months ago - Pushed at: about 3 years ago - Stars: 5 - Forks: 2

duskwuff/Xilinx-ISE-Makefile

An example of how to use the Xilinx ISE toolchain from the command line

Language: Makefile - Size: 8.79 KB - Last synced at: about 2 months ago - Pushed at: almost 6 years ago - Stars: 61 - Forks: 23

z1skgr/CalculatorVHDL

Design of the implementation of a calculator connected on the integrated FPGA

Language: VHDL - Size: 11.3 MB - Last synced at: about 2 months ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

Jamesits/verilog-basic-blocks

数电作业

Language: Verilog - Size: 120 KB - Last synced at: about 2 months ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 1

VLSIJEXA/basic-VHDL

VHDL Implementations:logic Gates, Flip-Flops, Adders, Mux, and Encoders/Decoder This repository contains VHDL implementations of essential digital circuits used in FPGA and ASIC design .This repository is useful for digital design projects and for understanding different VHDL modeling styles: behavioral, structural, and dataflow.

Language: C - Size: 8.52 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

v-i-s-h-n-u-b/Traffic-light-controller

FPGA implementation of North South, East West, Emergency Vehicle Response, Pedestrian Crossing - Verilog

Size: 70.3 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

v-i-s-h-n-u-b/8-bit-CPU

Simple CPU Design in Verilog with MIPS-like Architecture, featuring Branch Prediction and Interrupt Control.

Size: 89.8 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

Asterinos1/Neighbour-s-CPU-v2

This rep contains neighbour's cpu. Single-cycle / Multi-cycle CPU implementation in vhdl using ISE Xiling

Language: VHDL - Size: 5.96 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 2 - Forks: 0

ujjawalece/AES-and-DES-Implementation-in-Verilog-Xilinx-

Language: Verilog - Size: 14.1 MB - Last synced at: 4 months ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 0

islandcontroller/ArduinoXVC

Xilinx Virtual Cable (XVC) Server implementation for use with an Arduino UNO/Leonardo

Language: C++ - Size: 139 KB - Last synced at: 28 days ago - Pushed at: over 4 years ago - Stars: 8 - Forks: 2

unipieslab/sevax

Soft Error Vulnerability Analysis Framework for Xilinx FPGAs

Size: 33.3 MB - Last synced at: about 1 year ago - Pushed at: about 6 years ago - Stars: 3 - Forks: 0

Vanaub22/VHDL

These are VHDL codes that I wrote as a part of our Computer Architecture Course in the 4th Semester.

Language: VHDL - Size: 30.3 KB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

alessda/door_lock

Language: C - Size: 1.56 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

z1skgr/Tomasulo-BASED-processor

TOMASULO processor in VHDL implementation

Language: VHDL - Size: 14.7 MB - Last synced at: about 2 months ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0

PrayagS/MIPS_16bit

16-bit MIPS processor implemented in Verilog (as a part of Computer Organisation course)

Language: Verilog - Size: 3.97 MB - Last synced at: about 1 year ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 4

rv2442/16BitScientificCalculator

16 Bit Scientific Calculator Using Xilinx ISE 14.7 on Xilinx ISE, EDA Playground and Simple 4 bit calculator on Spartan 6 Board

Language: C - Size: 961 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 2

sahmad98/HardwareDesigns

Few of my VHDL hardware design for Xilinx Spartan 6 board

Language: VHDL - Size: 10.7 KB - Last synced at: about 1 year ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

hpaluch/crnr-ii-intro

Introductory Verilog project for Digilent CoolRunner-II Starter Board featuring Xilinx XC2C256-7-TQ144 CPLD

Language: HTML - Size: 2.13 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 1

Albocoder/SpartanElevator 📦

This is an elevator system with hardware queue made all in Verilog using Xilinx ISE.

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MaksymAndreiev/CompEngineering

Workshop on the course "Methods and Technologies of Computer Engineering" at V. N. Karazin Kharkiv National University

Language: VHDL - Size: 9.77 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

djjproject/spartan3_clock

VHDL Verilog / Clock on Spartan3 / 2014 University of Seoul

Language: C - Size: 6.48 MB - Last synced at: about 1 year ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0

Man2Dev/Logic-Circuits-and-Computer-Architecture-Lab-course

Some of my Logic Circuits and Computer Architecture Lab projects

Language: C - Size: 1.31 MB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Man2Dev/Computer-Architecture-course

Some of my Computer Architecture projects

Language: C - Size: 9.68 MB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

ViktorSlavkovic/FPGA_Tetris

FPGA Tetris written in Verilog

Language: Verilog - Size: 75.2 KB - Last synced at: about 1 year ago - Pushed at: about 7 years ago - Stars: 7 - Forks: 2

Subhankar2000/Xilinx-ISE-9.2i-EC792-VLSI-LAB

saving lab experiments in this repo, specific to MAKAUT ECE-2021 7th SEM(old syllabus)

Language: C++ - Size: 8.66 MB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

Saadia-Hassan/8x8Multiplier-Using-Vedic-Mathematics

An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

Language: Verilog - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 5 - Forks: 2

vinayak1998/Multiplier-Design

Language: VHDL - Size: 1.16 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

vinayak1998/Reflex-Tester

This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.

Language: VHDL - Size: 1.02 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 4 - Forks: 0

vinayak1998/7-segment-display-fpga

Design and implement a Seven Segment Display available on the BASYS3 board (FPGA) in VHDL

Language: VHDL - Size: 455 KB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 0

Subhankar2000/Xilinx-ISE-8.2i-EC792-VLSI-LAB

saving lab experiments in this repo, specific to MAKAUT ECE-2021 7th SEM(old syllabus)

Language: VHDL - Size: 13.8 MB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

MelvinMo/HDL_Course_Archive

This repository houses my work from the undergraduate hardware description language course in Verilog and the utilization of tools such as ModelSim and Xilinx ISE.

Language: Verilog - Size: 2.21 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

amirsoleix/Mano-system-architecture

Full implementation of Mano system architecture with VHDL using Xilinx ISE.

Language: C - Size: 1.71 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

maazm007/100Daysof_RTL

The Repository contains the code of various Digital Circuits

Language: Verilog - Size: 20.6 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 7 - Forks: 1

al45tair/pipistrello-TOSlink

TOSLink fibre data capture for Pipistrello (Xilinx SPARTAN 6)

Language: Verilog - Size: 214 KB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 1

JAYRAM711/100-DAYS-OF-RTL

This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools

Language: Verilog - Size: 40 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 12 - Forks: 1

JavadZandiyeh/AUT-LD-Lab

AUT Logic Design Lab

Language: Verilog - Size: 598 KB - Last synced at: almost 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 1

lorenzozaccomer/iterative-multiplier

Project for Electronic Calculators course.

Language: VHDL - Size: 4.77 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

ctsiaousis/mipsMultiCycleProcessor 📦

A VHDL implementation of a MIPS processor with multicycle instruction fetching

Language: C - Size: 1.36 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 0

Venkaraddi7/Elevator_Controller

To implement the elevator controller, we used Verilog as HDL. The focus of our project was the implementation and verification of a controller for a basic elevator functionality. We also proposed a methodology that utilizes the SCAN algorithm to enhance the efficiency and reliability of the controller.

Language: Verilog - Size: 1.58 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

maazm007/Xilinx-ISE

This is the collection of Schematics of various digital electronics elements, verilog codes and test benches of different operation and circuits

Language: C - Size: 1.86 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0

teekamkhandelwal/Uart_tx_main

Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate through digital pin 0, digital pin 1.

Language: Verilog - Size: 17.6 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

tarlaun/CORDIC

Digital System Design Project - Spring 2020

Language: Verilog - Size: 4.24 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 0

pontazaricardo/Verilog_Calculator_Matrix_Multiplication

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

Language: Verilog - Size: 3.73 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 34 - Forks: 8

maazm007/ALU-8-Bit-Adder

This is a basic project of Arithmetic Logic Unit that takes two input of 8 Bits each and undergoes 8 different operations and generates an output of 16 Bits

Language: C - Size: 918 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

maazm007/4_Bit_Signed_Calculator

Hardware Schematic of Four Bit Signed Calculator designed using Xilinx ISE 14.7

Language: C - Size: 1.56 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

zpekic/sys9080

Simple system built around VHDL implementation of Am9080 8-bit CPU based on 29XX bit-slice series of devices, as described here: https://en.wikichip.org/w/images/7/76/An_Emulation_of_the_Am9080A.pdf

Language: VHDL - Size: 112 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 6 - Forks: 1

baatochan/DigitalAndEmbeddedSystems 📦

VHDL projects done in Xilinx ISE Design Suite during Digital and Embedded Systems course (Układy Cyfrowe i Systemy Wbudowane 1) at the university.

Language: VHDL - Size: 5.82 MB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

kutayeroglu/two-player-minesweeper 📦

Simulation of the classic mine sweeper game on a SPARTAN 3A FPGA board. *Term Project for Digital Design course

Language: VHDL - Size: 404 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0

mcagriaksoy/VHDL-FPGA-LAB_PROJECTS

My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)

Language: VHDL - Size: 575 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 14 - Forks: 2

andrsmllr/spartan3e_starter_devbrd

Play and learn with the Digilent Spartan3E-Starter board featuring a Xilinx Spartan-3E XC3S500E FPGA and various peripherals.

Size: 2.93 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 1

kaushanr/System-Bus-Design

Design of a system bus architecture - Team Project @ ENTC UoM

Language: Verilog - Size: 10.1 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 2

mesarcik/MANDELBROT

A Verilog based Fractal Set Generator for the Xilinx Artix 7

Language: Verilog - Size: 29.3 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 7 - Forks: 3

PARSA-MHMDI/design-ALU-with-Xilinx-ISE

This is Amirkabir University Logic Circuit Design final project 2022

Language: C - Size: 8.2 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

manish257/Displaying-on-Seven-Segment-of-FPGA-using-Verilog

Language: HTML - Size: 438 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

SunkeerthM/MIPS-32

Implementation of the MIPS architecture in VHDL using Xilinx ISE 14.7 on the Spartan-3E board. Reference Website: https://www.d.umn.edu/~gshute/mips/MIPS.html; https://www.cise.ufl.edu/~mssz/CompOrg/CDA-proc.html

Language: VHDL - Size: 17.6 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

zpekic/tinycomputer

Tiny 4-bit CPU using AMD2901 bit slice (https://github.com/Amrnasr/AM2901) and program memory initialized from a file

Language: VHDL - Size: 616 KB - Last synced at: about 2 years ago - Pushed at: about 8 years ago - Stars: 8 - Forks: 1

MaharshSuryawala/Microprocessor-Without-Interlocked-Pipeline-Stages-MIPS

RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.

Language: Verilog - Size: 5.53 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1

SMATEO49/Project-of-Painting-Robot

My own project in VHDL using ISE Xilinx and FPGA component xc3s200-5ft256

Language: C - Size: 1.28 MB - Last synced at: about 2 months ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 1

alperklnc/two-player-minesweeper

Simulation of the classic mine sweeper game on a SPARTAN 3A FPGA board. *Term Project for Koç University ELEC 204: Digital Design course

Language: VHDL - Size: 475 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

akshay-na/Carry-Speculative-Adders

Pre-Final Year Engineering project where we designed and simulated optimized speculative adders.

Language: C - Size: 914 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 1

akshay-na/32-Bit-RISC-Architecture-Based-on-MIPS

Design and Simulation of High Performance 32-Bit RISC Architechture Based on MIPS (Still under teting)

Language: Verilog - Size: 155 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

Msiavashi/DES

DES encryption implemented on FPGA using verilog

Language: C - Size: 1.48 MB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 2 - Forks: 0

SamuelGong/SingleCycleCPU

A single cycle CPU running MIPS instructions on Xilinx FPGA

Language: Verilog - Size: 113 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 5 - Forks: 0

MossbauerLab/MessbauerTestEnvironment

FPGA Messbauer hardware (generator, emulation of signal from gamma-source registered and amplified

Language: Verilog - Size: 2.84 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 1

zpekic/alarmclock

12hr/24hr alarm clock with display dimming showcasing Mercury+Baseboard hardware (http://www.micro-nova.com/)

Language: VHDL - Size: 185 KB - Last synced at: about 2 years ago - Pushed at: about 8 years ago - Stars: 2 - Forks: 0

zpekic/sys_primegen

Signed / unsigned multiplier / divider used by a microcode-driven prime number generator

Language: VHDL - Size: 1.78 MB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 3 - Forks: 0

3ZadeSSG/VLSI-VHDL-Programs

VHDL Program Examples

Language: HTML - Size: 678 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

rosswelltiongco/CPU

Language: HTML - Size: 32.6 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

haoyang-graphics/cyber-melody-2

Cyber Melody 2 on MIPS!

Language: Verilog - Size: 3.64 MB - Last synced at: 23 days ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

susiejojo/Sobel_filter

Sobel filter for edge detection in images supporting parallel processing using Verilog on Xilinx ISE 13.4

Language: C - Size: 8.12 MB - Last synced at: about 1 month ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 1

SamuelGong/MultipleCycleCPU

A multiple cycle CPU running MIPS instructions on Xilinx FPGA

Language: Verilog - Size: 118 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 0

SamuelGong/MicroprogrammingProcessor

Microgramming technology applied to my multiple cycle CPU

Language: Verilog - Size: 119 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 1

muralikarteek7/KRSSG-FPGA

Language: C - Size: 18.5 MB - Last synced at: 6 months ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 2

vballoli/MIPS-Pipelined

Implementation of a model of pipelined MIPS processor in Verilog

Language: C - Size: 1.01 MB - Last synced at: about 2 months ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

AlmuHS/VHDL-Binary-Clock

Binary Clock adapted for Papilio One 500K. Show hours, minutes and seconds using binary system

Language: VHDL - Size: 338 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 1

JiriS97/BLOS-Projects

Working projects from BLOS lessons on Brno University of Technology

Language: VHDL - Size: 5.55 MB - Last synced at: 6 months ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

ismenc/fpga-vga-driver-game

This is 'space invaders' game and VGA driver builded on Xilinx ISE + Spartan 3

Language: VHDL - Size: 1.75 MB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0