GitHub topics: logic-design

Repositories

antoniossaliba/logic-controlled-board

A dynamic logic-controlled board using FSMs, LED sequences, and switch behavior with cap-detection logic.

Size: 3.69 MB - Last synced at: about 21 hours ago - Pushed at: about 21 hours ago - Stars: 0 - Forks: 0

mazidzomader/CSE260-BRACU

DIGITAL LOGIC DESIGN

Language: C++ - Size: 80.6 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

GawaliGanesh123/Logic-Building-Assignments

This repository contains Solutions to 50 assignments from the Logic Building batch at Marvellous Infosystems. Each assignment includes 5 problems covering topics such as Numbers, Digits, Arrays, Strings, Bits, Pattern Printing, File handling, and Data structures. These problems helped me develop strong problem-solving skills.

Language: C - Size: 1.58 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 0 - Forks: 0

asyncvlsi/chp2prs

Automated conversion from CHP to PRS using syntax-directed translation

Language: C++ - Size: 5.57 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 7 - Forks: 6

DrWaleedAYousef/Teaching

Teaching Materials for Dr. Waleed A. Yousef

Language: Mathematica - Size: 157 MB - Last synced at: about 1 month ago - Pushed at: 11 months ago - Stars: 1,004 - Forks: 319

ericm/newlogic

Circuit Builder Desktop Application (like mmlogic) made with Electron + React Typescript. Compatible with Windows, Mac and Linux.

Language: TypeScript - Size: 5.68 MB - Last synced at: 2 days ago - Pushed at: over 2 years ago - Stars: 32 - Forks: 3

venkat-0706/codemind-c

As an Ignite Coder, solved numerous problems using C programming, demonstrating expertise in algorithms, problem-solving, and efficient coding for technical challenges.

Language: C - Size: 182 KB - Last synced at: 30 days ago - Pushed at: 9 months ago - Stars: 11 - Forks: 0

RezaGooner/Karnaugh-Map

The program in GUI that show and minimize with Karnaugh-Map in Python & C++

Language: C++ - Size: 1.59 MB - Last synced at: about 2 months ago - Pushed at: 2 months ago - Stars: 3 - Forks: 0

dreylago/logicmin

Logic Minimization in Python

Language: Python - Size: 226 KB - Last synced at: 6 days ago - Pushed at: about 1 year ago - Stars: 24 - Forks: 7

kadircet/CENG

All the homeworks, testers and projects done at METU-CENG

Language: Jupyter Notebook - Size: 30 MB - Last synced at: 23 days ago - Pushed at: about 7 years ago - Stars: 18 - Forks: 5

Kowsalya2929/MemeVerse-App

MemeVerse-App

Language: JavaScript - Size: 191 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

VarshithGovi/2bit-Ripple-Carry-Adder-Verilog

A Verilog-based implementation of a 2-bit Ripple Carry Adder with a comprehensive testbench for functional verification, ideal for beginners exploring digital design and HDL concepts. 🚀

Language: Verilog - Size: 25.4 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

5y3b/Tabular-Method

Quine-McCluskey Minimization Technique (Tabular-Method) Digital Logic Design

Language: Python - Size: 5.86 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

3ein39/MultiSolver

The Idea is a gui program can solve most of the problems that faces students in courses like mathematics and physics And it also have another branch for helping the students with their time management and provide the students with materials

Language: C++ - Size: 104 MB - Last synced at: 2 months ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0

AhmedHamed3699/AES-Encryption

An AES encryption and decryption project that follows SPI (Serial Peripheral Interface) specification. Implemented in Verilog

Language: Verilog - Size: 208 KB - Last synced at: 3 months ago - Pushed at: almost 2 years ago - Stars: 6 - Forks: 2

ImRanjbar/TeachingAssistant-Resources

A collection of assignments, workshops, and educational materials created during my teaching assistant journey at the University of Isfahan.

Language: C++ - Size: 22.7 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 2 - Forks: 0

Abdulrahman-Mostafa10/3-bit-Calculator

Size: 54.7 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

jcdalbello/tp-diseno-logico-untref

Repositorio del trabajo practico de la asignatura de Diseño Logico de la UNTREF, 2024C2

Language: VHDL - Size: 1.15 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

michaelehab/Arithmetic-Logic-Unit-Project

Educational Project for Logic Design 1 course taken during Fall 2021 semester.

Size: 11.3 MB - Last synced at: 2 months ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 0

DopeBiscuit/IEEE-Digital-IC-Design

This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.

Language: Verilog - Size: 11.5 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 1

Mostafa-wael/SPI-Protocol

A digital design for the SPI protocol, delivered as a project for the logic design course

Language: Verilog - Size: 2.51 MB - Last synced at: about 2 months ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 2

devKanix/Star-Pattern-problem-solving

Star-Patterns-problem-solving: A collection of Java programs to create various star patterns. Perfect for beginners to practice loops and nested loops in Java.

Language: Java - Size: 2.93 KB - Last synced at: 2 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

paolopedroso/Stop-It-Game

Created a state machine for a sequential circuit game called "Stop It," which is programmed onto a Basys 3 FPGA Board. The project emphasizes understanding state machines, sequential circuits, and FPGA.

Language: SystemVerilog - Size: 316 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

abdosalem490/ComputeHub

this is a project made whne i was in college for a subject called logic 1

Size: 6.64 MB - Last synced at: 9 months ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

abdosalem490/VerilogSPIController

this is a college project of making SPI interface using verilog

Language: Verilog - Size: 23.8 MB - Last synced at: 9 months ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

Moataz-mohsen/16-bit-microprocessor

16-bit microprocessor

Language: C - Size: 202 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

paolopedroso/Screensaver

This project focuses on implementing a VGA interface and a screensaver for the Basys 3 FPGA Board. It involves generating VGA signals to display images stored in ROM, showcasing how to control and synchronize video output. The project culminates in programming the FPGA to display a functional screensaver on a VGA monitor.

Language: Tcl - Size: 2.72 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

Noamv7/Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

Language: Verilog - Size: 30.2 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

akxavier/Assignments

B.Tech CSE @ NITC

Language: C - Size: 18.6 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

beetlex-io/EventNext

EventNext is logic interface design actors components for .net core

Language: C# - Size: 86.9 KB - Last synced at: 9 days ago - Pushed at: over 2 years ago - Stars: 42 - Forks: 10

krish1925/Texas-Holdem-Poker

Implementation of Texas Hold'em Poker on Verilog(Basys3 FGPA)

Language: Verilog - Size: 5.68 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

enesgarip/Projects

Projects of a CSE student at Marmara University

Language: Java - Size: 57.6 MB - Last synced at: 11 months ago - Pushed at: almost 3 years ago - Stars: 7 - Forks: 6

4FXhD9ZD1PDw/pure-vpnjRBP5fplbwsM

Size: 0 Bytes - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

shayanop/Pure-vpn

Pure-vpn

Size: 17.6 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 475 - Forks: 0

melanie-t27/Logic-Design-Project

Project for the Reti Logiche Course at @POLIMI, instructed by Prof. Gianluca Palermo during the academic year 2022/23

Language: VHDL - Size: 1.02 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

dhwanish-3/Verilog-Programming-Logic-Design-Lab

Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator

Language: Verilog - Size: 28.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

muratizm/SIGANFU

MK-LMC SIGANFU Tactical Power Armor - Final Verilog Project of Logic Design

Language: Verilog - Size: 1.77 MB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

VitorgsRuffo/Building-The-Hack-Computer

This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.

Language: Scilab - Size: 281 KB - Last synced at: 12 months ago - Pushed at: over 3 years ago - Stars: 10 - Forks: 2

lucas89901/ntu-scld-2023-fall-quartus-lab 📦

Quartus Lab assignments of NTU EE's switching circuit and logic design course (2023 fall).

Language: Verilog - Size: 18.1 MB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

heckerfr0d/LD_LAB

VARILAG LAGIK

Language: Verilog - Size: 2.08 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

Aswin-Koroth/Logic-Lab

Logic gates simulator with vanilla javaScript

Language: JavaScript - Size: 275 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

abotaha23/3BitCalculator Fork of ahmedibrahim404/3BitCalculator

This project is implemented upon Logic Design I Course

Size: 95.7 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

tunacinsoy/CSE

All the homeworks, testers and projects done at Marmara University, Computer Science & Engineering

Language: Java - Size: 17 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 7 - Forks: 0

kevin-rh/logic-design

2021 Fall EECS-2070 by Prof. 李濬屹 Team37 with @schdoel

Language: Verilog - Size: 8.04 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

ParhamP/Natural_Logic_Interpreter

Automatically interpret and validate nested natural logic arguments based on rules of inference and propositional logic

Language: Python - Size: 121 KB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 117 - Forks: 10

n1colasf/Obligatorio-DDA

Obligatorio Diseño y Desarrollo de Aplicaciones (Semestre 4 - Marzo 2023) Calificación: 36/40

Language: Java - Size: 1.06 MB - Last synced at: 4 days ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 0

ferhatozkan/Digital-Logic-Design-Project

University of Marmara, CSE3015 2018 Fall Project

Language: Java - Size: 2.6 MB - Last synced at: almost 2 years ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 0

geitanksha/risc-v-pipelined

Created a RISC-V Pipelined processor in SystemVerilog with features like Caches, Prefetching, History Table. Skills employed: SystemVerilog, Verdi, Logic Design, Computer Architecture

Language: HTML - Size: 5.43 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Marwan-9/digital-logic-circuits-simulator

A Windows application for designing and simulating digital logic circuits, written in C++ using CMU graphics library.

Language: C - Size: 14.5 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

matchy-at-snu/logic-design-lab

🍟 Logic Design Verilog practice

Language: Verilog - Size: 67.9 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

Pixailz/logic_stuff

logic stuff, diagrams, notes, images etc

Size: 4.39 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

YoussefMouaddib/Raspberry-Pi-Direct-Register-Robot-Maze-solver-

This program is the software part of a Robot Line Maze-solver Project. Implemented on a raspberry pi using Direct-Register Control on Raspberry Pi. This project was made in attempt to get a better grasp of the following topics: Kernels and Linux, Direct-Register Control, Recursive Algorithms, Logic Design, Solidwork and 3D printing

Language: C - Size: 36.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

mohamedgamalmoha/Memory-Unit-as-Logic-Design

16x12 Memory Unit Logic Design Using Logisim

Size: 71.3 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

anthonyabeo/digital_circuits

A collection of digital logic circuits

Language: SystemVerilog - Size: 54.7 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 5 - Forks: 3

andresrodriguez55/aSimple8-BitProcessor

Simple microprocessor in SystemVerilog.

Language: C - Size: 2.11 MB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 0

harisrab/logicSim_ANN

A Logic Gate Simulator Using Artificial Deep Neural Networks

Language: Python - Size: 60.8 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

mohamedhassan279/4bit-BCD-Counter

4-bit BCD up/down counter.

Language: VHDL - Size: 1.95 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

mohamedhassan279/4bit-Ripple-Adder-Subtractor

4 bit ripple adder, which adds 2 4-bit inputs introducing sum and carry signals. Implement the following modules: 1. Half adder. 2. Full adder using the half adder. 3. 4-bit ripple adder/subtractor using the full adder.

Language: VHDL - Size: 17.6 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

mohamedhassan279/Even0-Even1

A continuous state diagram that outputs 1 when it receives an even number of 0s or even number of 1’s.

Language: VHDL - Size: 2.93 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

ysyesilyurt/Metu-CENG

All the homeworks, studies and projects I've done at Metu-CENG

Language: Jupyter Notebook - Size: 73.1 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 41 - Forks: 9

stdgregwar/elve

ELVE : ELVE Logic Visualization Engine

Language: C++ - Size: 2.62 MB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 8 - Forks: 0

Hoda233/Logic-Design_arithmetic-unit-project Fork of norhanreda/CMP1010_Logic-Design_arithmetic-unit_project

Logic Design for ALU

Size: 37.1 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

Hoda233/SPI Fork of norhanreda/SPI

Master-Slave Interface.

Language: Verilog - Size: 2.38 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

emredogan7/metu-ee

Includes some assignments/reports belonging to the courses attended during my BSc degree.

Language: Matlab - Size: 33.9 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0

gsmitheidw/Digital

Chocolatey nupkg recipe for Digital logic designer and circuit simulator

Language: PowerShell - Size: 33.2 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

saifmohammednipun/digital-logic-design

This course provides an introduction to logic design and basic tools for the design of digital logic systems.

Size: 242 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

nevikw39/LogicDesignLab

EECS207001

Language: Verilog - Size: 14.6 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

nevikw39/LogicDesign

11020EECS101002

Language: Verilog - Size: 1.28 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Marwan-9/arithmetic-unit-logisim

An arithmetic unit circuit capable of adding, subtracting and multiplying two signed magnitude numbers, implemented using Logisim.

Size: 574 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

barishazar3431/CSE3015-Processor-Design-in-Logisim

A Simple Processor, Designed Using Logisim Software

Language: Java - Size: 596 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Daniyar1239/Electronic-dice-and-counter

Electronic dice, two-bit adder and counter made from logic gates in Multimedia Logic software

Size: 349 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

CrypticMessenger/Encryption-Decryption-using-MM

modelled encryption-decryption module using verilog. Given a text file, it can be encrypted using encryptor and can be decrypted later using decryptor.

Language: Verilog - Size: 493 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 1

DPhongUIT2021/Verilog

Language: HTML - Size: 6.05 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

ZeyadTarekk/Carry-Select-Adder

Carry Select Adder Using verilog

Language: Verilog - Size: 194 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

ZeyadTarekk/Combinational-Multiplier

Combinational Multiplier Using verilog

Language: Verilog - Size: 826 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 0

matiasmicheletto/simcirjs Fork of kazuhikoarase/simcirjs

A SimCirJS fork with enhanced functionalities

Language: JavaScript - Size: 2.85 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 1

abrarrhine/Digital-Logic-Design

Logic design homework using AND, OR, XOR for Computer Organization class.

Size: 224 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

hebaashraf21/Serial-Peripheral-Interface

Design and implementation the components of the SPI modules: Master, Slave and Self-Checking Testbenches for the Master and Slave. using verilog

Size: 0 Bytes - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 1

hebaashraf21/Execution-Unit

An execution unit that is able to do the following commands: Move Value to Register, Move Register to Register, Add Value to Register, Add Register to Register, AND Value to Register and AND Register to Register.

Size: 48.8 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 1

hebaashraf21/Arithmetic-Logic-Unit

It is an arithmetic unit that is capable of adding, subtracting and multiplying two signed magnitude numbers, and displays the result of the operation performed along with some additional flags regarding the operation and the result.

Size: 57.6 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

arashsm79/two-bit-multiplier

Two's complement two bit multiplier developed in Proteus

Size: 1.63 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 0

fcayci/sv-digital-design

SystemVerilog examples for a digital design course

Language: SystemVerilog - Size: 29.3 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 9 - Forks: 9

menna15/Randomizer

Using a linear feedback shift register (LFSR), design a pseudorandom binary sequence (PRBS) generator.

Language: Verilog - Size: 17.6 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0

nnakul/IITKGP-CSE-Sem04

The repository contains all the assignments completed as a course-work of the 4th semester.

Language: C++ - Size: 25.2 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

JoseDavidSS/DL.HammingCode

Primer proyecto para el curso de Diseño Digital. La idea es hacer una aplicación referente al código Hamming utilizando el lenguaje de programación Python.

Language: Python - Size: 29.3 KB - Last synced at: about 2 months ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

hesham-medhat/Opti-Circuit

This software is designed to help Computer/Electric Hardware Engineers design an efficient digital logic circuit with best optimisation for lowest cost and power consumption to implement any function.

Language: Java - Size: 2.54 MB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 1 - Forks: 1

ZeyadTarekk/ALU Fork of Abd-ELrahmanHamza/ALU

Design and implementation an arithmetic unit that is capable of adding, subtracting and multiplying two signed magnitude numbers, and displays the result of the operation performed along with some additional flags regarding the operation and the result using Logisim.

Size: 1.29 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0