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GitHub / dhwanish-3 / Verilog-Programming-Logic-Design-Lab

Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dhwanish-3%2FVerilog-Programming-Logic-Design-Lab

Stars: 0
Forks: 0
Open issues: 2

License: mit
Language: Verilog
Size: 28.3 KB
Dependencies parsed at: Pending

Created at: about 1 year ago
Updated at: about 1 year ago
Pushed at: about 1 year ago
Last synced at: about 1 year ago

Topics: intel-fpga, logic-design, modelsim, verilog, verilog-code, verilog-hdl, vlsi-design

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