GitHub topics: vlsi-design
DuttPanchal04/6t-sram-cell-cmos-design-electric-vlsi-tool
This project demonstrates the **design of a 6-Transistor (6T) SRAM memory cell** using the **Electric VLSI Design System**. It includes only the **schematic and layout**—simulation and waveform outputs are not included in this repository.
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amitops2103/Verilog-Assignment
Verilog practice sessions by Mr. Sujit Panda
Language: Verilog - Size: 904 KB - Last synced at: about 12 hours ago - Pushed at: about 12 hours ago - Stars: 1 - Forks: 1
DuttPanchal04/rtl-design-and-synthesis-using-icarus-verilog-gtkwave-yosys
A collection of Verilog-based RTL design projects with testbenches, simulated using Icarus Verilog and GTKWave. This repo showcases foundational digital logic circuits as part of my VLSI learning journey using open-source tools.
Language: Verilog - Size: 6.52 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0
BegangLive/VLSI-Design-Verification-Projects
This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects
Language: Stata - Size: 20.5 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0
ab-ff/Multi-Bit-Comparator
Variations of a multi-bit generalized comparator for different area and timing.
Size: 1000 Bytes - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0
Axat-Gadhwal/VSD-Boards-Research
Created for reviewing VSD Boards and creating different projects. Stay tuned!
Language: Verilog - Size: 16.6 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 0
luarss/awesome-conference-dates
VLSI Conference Dates
Language: Python - Size: 11.9 MB - Last synced at: about 20 hours ago - Pushed at: about 21 hours ago - Stars: 1 - Forks: 0
Axat-Gadhwal/VSD-Squadron-FM-Research-Internship
This repo is created by Axat Gadhwal of grade 7th of APS Varanasi.
Language: Verilog - Size: 10.2 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 1 - Forks: 0
sc0puli/HighLevel
This repo contains labs for course High level design and verification languages
Language: Python - Size: 21.5 KB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 0 - Forks: 0
pasambaladitya123/SURE-trust_vlsi-project-vending-machine
Verilog-Based Vending Machine Controller This project implements a scalable, real-time vending machine controller using Verilog HDL. It features modular FSM design, APB-based configuration, asynchronous input handling, and clock domain synchronization between 10 MHz and 100 MHz domains. The system supports up to 1024 items with configurable prices
Language: Verilog - Size: 3.91 KB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 0 - Forks: 0
RarityBrown/blog
Some ramblings about my major. 一些有关我的专业的碎碎念
Size: 797 KB - Last synced at: 22 days ago - Pushed at: 22 days ago - Stars: 2 - Forks: 0
Preven-K/Vending-Machine
Language: Verilog - Size: 101 KB - Last synced at: 22 days ago - Pushed at: 23 days ago - Stars: 0 - Forks: 0
SACHINUR17/VLSI-Design-Verification-Projects
This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects
Language: Stata - Size: 23.4 KB - Last synced at: 23 days ago - Pushed at: 23 days ago - Stars: 1 - Forks: 0
pesadaum/pesadaum
Sobre mim
Size: 49.8 KB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 4 - Forks: 0
Kethasriramya2912/Btech_Projects
I've delved into leveraging my academic prowess to drive projects that contribute to my career advancement.
Language: SystemVerilog - Size: 20.8 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
SKpro-glitch/RISCV-Processor-ASIC
This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
Language: Verilog - Size: 138 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
SKpro-glitch/Multi-Bit-Comparator
Variations of a multi-bit generalized magnitude comparator for different area and timing.
Language: Verilog - Size: 33.2 KB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
FarhanTips/VLSI-Design
This repository covers VLSI Design concepts using Microwind, Quartus, and Waveforms, focusing on digital circuit design, FPGA implementation, and HDL for integrated circuit development.
Size: 932 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0
rishabhjain7b/HLS-Scratchpad
Small designs made using Catapult-based HLS (C++ / SystemC)
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Kethasriramya2912/Verilog-RTL-Coding
"Mastering RTL-Coding : From Fundamentals to Advanced Programming Techniques using Verilog,System Verilog and UVM"
Language: Verilog - Size: 64.5 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 3 - Forks: 0
meiniKi/FazyRV
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Language: SystemVerilog - Size: 772 KB - Last synced at: about 2 months ago - Pushed at: 8 months ago - Stars: 89 - Forks: 4
brahad316/FAN-ATPG
an implementation of the FAN ATPG algorithm in c++ and verilog.
Language: C++ - Size: 156 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0
lip6/alliance-check-toolkit
Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)
Language: Python - Size: 371 MB - Last synced at: 5 days ago - Pushed at: 11 days ago - Stars: 12 - Forks: 3
0xIsagiY9/College-4th-FirstTerm
Senior Year - First Term - Faculty of Engineering Helwan University - Repository
Size: 548 MB - Last synced at: about 1 month ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
SKpro-glitch/Parallel_Multiplier
Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
Language: SystemVerilog - Size: 13.7 KB - Last synced at: about 1 month ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0
VarshithGovi/Half-Subtractor-Design-Verilog
Gate-level implementation of a half-subtractor using Verilog, featuring a comprehensive testbench, truth table validation, and waveform analysis for beginners in digital design.
Language: Verilog - Size: 20.5 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
AdarshMishra26/SCL-Project
This is the Repository which contains the detail of my work done at SCL Mohali (formerly Department of Space, ISRO). This was the internship basically focused on the "Experimental Analysis of MOS Capacitor for Oxide Furnaces" and further study of VLSI.
Language: HTML - Size: 3.27 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0
VarshithGovi/Full-Adder-Design-Verilog
Gate-level implementation of a full-adder using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.
Language: Verilog - Size: 11.7 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
soham9284/100_Days_of_Verilog
Language: Verilog - Size: 3.57 MB - Last synced at: about 1 month ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0
DarrenHuang0411/Verilog-Training-Pipeline-CPU
Verilog-Training-5-stage-Pipeline-CPU
Language: SystemVerilog - Size: 1.46 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0
Abdulrahman-Mostafa10/Synopsys-Chip-Design
Language: Verilog - Size: 8.54 MB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 3 - Forks: 1
VarshithGovi/2-to-1-Multiplexer-Design-Verilog
Gate-level implementation of a 2-to-1 multiplexer using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.
Language: Verilog - Size: 17.6 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0
Abdulrahman-Mostafa10/VLSI_Labs
This repository contains my work along for my academic VLSI course 🚀
Language: Tcl - Size: 19.2 MB - Last synced at: 3 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0
LijinWilson/CMOS-NAND-gate-2-input-NAND-gate
This repository contains the design, simulation, and performance evaluation of a CMOS NAND Gate using Cadence Virtuoso. The project highlights the design principles and operational characteristics of a fundamental digital logic gate implemented with CMOS technology.
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LijinWilson/traffic-light-controller
Traffic Light Controller This repository showcases the design and implementation of a Traffic Light Controller using Verilog. The project simulates a real-world traffic management system, ensuring smooth vehicle movement at intersections through an efficient state-based control mechanism.
Language: Verilog - Size: 35.2 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0
synogate/gatery
Gatery, a library for circuit design.
Language: C++ - Size: 8.29 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 17 - Forks: 5
nwad123/A-star_Global_Router
My A* global routing solution for ECE 5460 - VLSI Design Automation
Language: C++ - Size: 7.53 MB - Last synced at: about 2 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0
rohankalbag/vlsi-design
VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay
Language: VHDL - Size: 5.68 MB - Last synced at: 2 months ago - Pushed at: about 2 years ago - Stars: 7 - Forks: 0
teekamkhandelwal/SRAM_Controller
The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.
Language: Verilog - Size: 72.3 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0
krutideepanpanda/RISC-V-based-micro-controller-using-OpenLane
This is part of EC383 - Mini Project in VLSI Design.
Language: Verilog - Size: 16.6 MB - Last synced at: 3 months ago - Pushed at: about 3 years ago - Stars: 8 - Forks: 0
synogate/gatery_template
Template project for using gatery
Language: C++ - Size: 22.5 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 4 - Forks: 1
VLSIJEXA/basic-VHDL
VHDL Implementations:logic Gates, Flip-Flops, Adders, Mux, and Encoders/Decoder This repository contains VHDL implementations of essential digital circuits used in FPGA and ASIC design .This repository is useful for digital design projects and for understanding different VHDL modeling styles: behavioral, structural, and dataflow.
Language: C - Size: 8.52 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0
AnitaSoroush/CircuitPartitioning-GNN
This is my MSc thesis project published in the University of Guelph library. This project applies Graph Neural Networks, to an optimization problem, Circuit Partitioning, leveraging, the predictive power of deep learning instead of traditional techniques.
Language: Python - Size: 293 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0
kanndil/PODEM-ATPG
Path-Oriented Decision Making (PODEM) algorithm for Automatic Test Pattern Generation (ATPG).
Language: Python - Size: 112 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
ucerd/Summer-School-2023_2
Summer School on Full Stack Open-Source Ecosystem for Processor Based Chip Design
Size: 59.3 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
ADolbyB/vlsi-spice-pcbs
A collection of Schematics, PCBs and VLSI work on various platforms
Language: C++ - Size: 6.26 MB - Last synced at: about 2 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0
Sajitha-Madugalle/cmos_inverter_sky130 Fork of SkillSurf/cmos_inverter_sky130
The repository contains an analysis and tapeout design process of a CMOS inverter under sky130 PDK. open source tools like Ngspice, Magic VLSI, Xschem has been used for design and simulations.
Size: 2.17 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0
srohit0/mida
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
Language: Jupyter Notebook - Size: 11.9 MB - Last synced at: 26 days ago - Pushed at: over 6 years ago - Stars: 26 - Forks: 7
SathyasriS27/VLSI_Design
Repository containing the simulated schematics of logic gates, counters, adders and registers along with corresponding layouts for semiconductor design.
Size: 71.3 KB - Last synced at: 2 months ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0
limbo018/Limbo
Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
Language: C++ - Size: 43.6 MB - Last synced at: 9 months ago - Pushed at: over 1 year ago - Stars: 137 - Forks: 50
tharunchitipolu/Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
Language: Verilog - Size: 19.5 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 32 - Forks: 6
maazm007/vsdsquadron-mini-internship
VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
Language: C - Size: 5.79 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 5 - Forks: 0
mrsamsonn/vlsi-project
VLSI Project for CMPE 480______ Authors: John San Juan, Cody Hum, Vincent Verdan, Jose Zaragosa
Language: Batchfile - Size: 5.86 MB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
the-pinbo/EC302-VLSI-Design-Lab
EC302-VLSI-Design-Lab
Language: Roff - Size: 4.3 MB - Last synced at: 3 months ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
1rsh/EC39004
This repository contains code files for VLSI Laboratory - EC39004, conducted in Spring 2024 at IIT Kharagpur
Language: Verilog - Size: 4.23 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
mehadihn/BRACUCSE460
BRACU CSE460 Lab (Summer 2020)
Language: Scheme - Size: 37.8 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0
neeraj1397/A-Primer-For-Physical-Design-Automation
This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
Language: Jupyter Notebook - Size: 782 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 1
dhwanish-3/Verilog-Programming-Logic-Design-Lab
Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator
Language: Verilog - Size: 28.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
Valendrew/vlsi-design
Combinatorial and Decision Making Optimization (CDMO) project during the A.Y. 2021/2022.
Language: Python - Size: 6.05 MB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 2
FarshidKeivanian/Optimum-Layout-of-Multiplexer-with-Minimal-Average-Power-based-on-IWO-Fuzzy-IWO-GA-and-Fuzzy-GA
FuzzyIWO-Algorithm (Adaptive fuzzy optimisation algorithm)
Language: MATLAB - Size: 368 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 1
FarshidKeivanian/Minimization-of-Average-Power-Consumption-in-3-Stage-CMOS-Ring-Oscillator-based-on-MSFLA-Fuzzy-MSFL
FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)
Language: MATLAB - Size: 815 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 2
efabless/ravenna
32-bit RISC-V microcontroller
Language: C - Size: 2.14 MB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 11 - Forks: 6
VardhanSuroshi/Vedic-Multiplier-From-RTL2GDS
GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA
Language: Verilog - Size: 6.6 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
VardhanSuroshi/VLSI-ASIC-Design-Flow
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
Language: Verilog - Size: 2.93 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
shobhit-mittra/RTL-to-GDS2-flow
This repository is my attempt to get a hands-on-experience on the VLSI flow using Open-Source EDA tools.
Size: 939 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
mj1069/testbench-system-verilog
SystemVerilog verification of I2C interface
Language: SystemVerilog - Size: 7.81 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Domain Specific Hardware Accelerators - VLSI CAD Project
Language: Bluespec - Size: 4.59 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 2
shobhit-mittra/vco-analysis
This project is a part of the report for my 7th semester program elective (EC-4142 Analog-VLSI).
Size: 538 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
ads930/4_bit_adder
This is a 4-bit pipelined carry-ripple adder. The design has been optimized for delay. To view the project, download the zip file and open the project in Cadence Virtuoso.
Size: 281 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 0
ishaanjoshi03/VGA_System
VLSI System with memory that displays arithmetic operations on a Video Graphics Array. (October 2023)
Language: VHDL - Size: 10.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
Saadia-Hassan/Types-of-Verification-Using-SRAM
This repo contains golden vector and randomization testbenches for SRAM module.
Language: Verilog - Size: 7.81 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 2
SCOUT-ELITE/H.264_Decoder
Introducing an innovative H.264 decoder project with QCIF resolution, designed to enhance video playback performance. This open-source GitHub repository offers a robust solution for decoding H.264 video streams, enabling seamless playback on various platforms.
Language: Verilog - Size: 80.5 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
123-r-ajay/sr_latch
implementing the sr_latch layout
Size: 730 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
souradipp76/Hamming_Distance_Calculator
This is a vlsi design of a hamming distance calculator circuit.
Language: SourcePawn - Size: 15.5 MB - Last synced at: over 1 year ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 1
shandilyaguy247/ECE3002_VLSI_System_Design
Contains all the necessary lab tasks (Cadence Virtuoso) for ECE3002 VLSI System Design (VIT).
Size: 4.15 MB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0
maazm007/100Daysof_RTL
The Repository contains the code of various Digital Circuits
Language: Verilog - Size: 20.6 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 7 - Forks: 1
paripath/cdf
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
Language: C++ - Size: 510 KB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 12 - Forks: 4
MrTejas/4-bit-multiplier
Design, Layout and performance analysis of a simple 4x4 multiplier circuit simulated in ngspice with power and time-delay calculations.
Language: Raku - Size: 505 KB - Last synced at: 3 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
ekb0412/100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
Language: Verilog - Size: 12 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 9 - Forks: 1
aesthet1c0der/Verilog-projects
ALU (Arithmetic and Logic Unit), Ripple carry adder, Half adder and full adder are designed using all 3 styles (structural, behavioral, dataflow) and tested by generating stimulus using testbench
Language: Verilog - Size: 21.5 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0
fightforit/SystemVerilog-Design-Blocks-Common-Use-Cases-and-Examples
Language: SystemVerilog - Size: 20.5 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
latticescipub/Indian-Journal-of-VLSI-Design-IJVLSID-
The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online) which is an online, open access, peer reviewed, periodical half yearly international journal.
Size: 2.93 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
karthik-r-rao/VLSI_Physical_Design_Tool
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
Language: Python - Size: 890 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 5 - Forks: 3
pratik2050/Learning-VLSI
VLSI Design using Vivado 2018
Language: JavaScript - Size: 693 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
the-pinbo/EC802-Low-Power-VLSI-Design
EC802 - Low Power VLSI Design
Language: Jupyter Notebook - Size: 4.42 MB - Last synced at: 3 months ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
twweeb/VLSI-Physical-Design-Automation
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
Language: C++ - Size: 57.3 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 22 - Forks: 10
NARDEEPsinghSHEKHAWAT/VERILOG-VLSI-CODES
Some codes I have implemented during my 10 day Training under VLSI DOMAIN
Size: 1000 Bytes - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
harsh-kmr/verilog_experiments
This repository is created for VLSI Experiments in Verilog for Engineering Sem 5 based on the Syllabus of IIIT Trichy. Here you can find the necessary codes, design files, and documentation for the experiments
Language: Rich Text Format - Size: 15.8 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0
OrsuVenkataKrishnaiah1235/System-Verilog
"Mastering SystemVerilog: From Fundamentals to Advanced Programming Techniques"
Language: SystemVerilog - Size: 10.7 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 1
thatbeautifuldream/vlsi-lab
vlsi lab experiments
Size: 1.35 MB - Last synced at: about 2 months ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0
hibagus/64pointFFTProcessor
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
Language: Verilog - Size: 29.8 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 13 - Forks: 7
vishalcseiitg/cs577-c-based-vlsi-design-project
Language: C - Size: 4.64 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
ahmedishraq/CSE460-Lab
CSE460 - VLSI Design
Language: HTML - Size: 5.81 MB - Last synced at: 28 days ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
maazm007/ALU-8-Bit-Adder
This is a basic project of Arithmetic Logic Unit that takes two input of 8 Bits each and undergoes 8 different operations and generates an output of 16 Bits
Language: C - Size: 918 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0
iamraufu/BRACUCSE460
VLSI Design - Spring 2022
Language: Verilog - Size: 4.08 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 0
zwhexplorer/Spiking-Neural-Network-Accelerator-EE552-project
Spiking Neural Network Accelerator
Language: SystemVerilog - Size: 1.65 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 4 - Forks: 1
akhileshmagdum/Maze-VLSI-Routing
Innovative way for path connection in VLSI.
Language: Python - Size: 2.93 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 1
sagniknitr/VLSI-Lab-Final-Year-Undergraduate-
This respositort contains all vhdl codes and simulations of final year vlsi lab of NIT Rourkela
Language: VHDL - Size: 3.23 MB - Last synced at: about 2 years ago - Pushed at: over 8 years ago - Stars: 2 - Forks: 1
maazm007/4_Bit_Signed_Calculator
Hardware Schematic of Four Bit Signed Calculator designed using Xilinx ISE 14.7
Language: C - Size: 1.56 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0
skynatepro/MIPS32
Design of 32-bit MIPS Processor
Language: Verilog - Size: 5.7 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0
