GitHub topics: dadda-multiplier
rohankalbag/vlsi-design
VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay
Language: VHDL - Size: 5.68 MB - Last synced at: 3 months ago - Pushed at: about 2 years ago - Stars: 7 - Forks: 0
tharunchitipolu/Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
Language: Verilog - Size: 19.5 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 32 - Forks: 6
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