GitHub topics: fulladder

Repositories

QabasAK/GLADE-FullAdder

Designed and tested a CMOS full adder using XOR, AND, OR gates, and an inverter, verifying functionality through DRC, LVS, LPE, and Spice3 simulations with NAND and GLADE implementations.

Size: 36.1 KB - Last synced at: 28 days ago - Pushed at: 28 days ago - Stars: 0 - Forks: 0

AnjanaSenanayake/verilog-model-for-4bit-alu

4 bit ALU in verilog

Language: Verilog - Size: 1.95 KB - Last synced at: about 2 months ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

Lopfi/8bit-adder

A DIY 8 Bit Adder from single transistors

Language: HTML - Size: 908 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

barannmeisterr/32-Bit-ALU-Design

This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic

Language: SystemVerilog - Size: 0 Bytes - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

mahdizynali/verilog-digital-circuit-codes

simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)

Language: Verilog - Size: 13.7 KB - Last synced at: about 2 months ago - Pushed at: almost 2 years ago - Stars: 8 - Forks: 1

tharunchitipolu/Dadda-Multiplier-using-CSA

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

Language: Verilog - Size: 19.5 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 32 - Forks: 6

shahed22/Dadda-8-bit

The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.

Language: Verilog - Size: 11.7 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

Mariam-Katamashvili/Veri-Simple

A collection of Verilog code examples, perfect for beginners or anyone looking to learn Verilog. These examples are based on my homework assignments from my university and include comments and explanations to help you understand the code better. Check out the link below for more information about Verilog!! 👇

Language: Verilog - Size: 20.5 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

salzhang/KoggeStone-Adder

A 32-bit Kogge-Stone Adder is implemented in this design.

Language: Verilog - Size: 93.8 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Saadia-Hassan/Simulation-of-Memristor-Based-Full-Adder

LTSpice simulation software is used to study the behavior of a Memristor. Different logic gates like NOR, NAND and XOR were modelled and simulated followed by the simulation of a memristor based full-adder.

Language: AGS Script - Size: 1.95 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 1

DevMajed/Digital-Logic_and-Design 📦

Digital Logic Design using pen and paper to design with Analog discovery 2, and using Verilog for synthesizing. these are some of my junior year labs for Digital Electronics

Language: Verilog - Size: 31.3 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 0

Artityagi123456789/Verilog_Practice_Code

Digital Design using Verilog

Language: Verilog - Size: 37.1 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

isabekov/FourBitSerialAdderSubtractor

4-bit Serial Adder/Subtractor with Parallel Load

Language: VHDL - Size: 12.7 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 2

gautamop01/Digital-Systems-and-Design

Learned as a part of CS210 course

Language: VHDL - Size: 16.6 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

ZeroDashZero/32-bit-Multiplier-design-using-transistor-level-Digital-Gates

This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert

Size: 6.57 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 5

MuballighHossain/Full_Adder_Priority_Encoder_VLSI

Language: Verilog - Size: 48.8 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 1

theoctober19th/full-adder-simulation

Simulation of full adder circuit to add two byte-sized integers in Python 3.

Language: Python - Size: 27.3 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0

anthony7586/designing-with-VHDL

porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation

Size: 30.1 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Frankline-Sable/4-Bit-Binary-Adder-and-Subtractor-Wire-Connections

➕➖ Arithmetic operations in most machines are performed in the ALU whereby logic gates and flipflops are combined so that they can subtract, multiply, and divide binary numbers. This circuit only implements the addition part and subtraction on four bit digits

Size: 373 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0