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GitHub topics: next-state-logic

anthony7586/designing-with-VHDL

porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation

Size: 30.1 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Related Keywords
adder-subtractor 1 battleship 1 battleship-game 1 delay 1 delay-propogation 1 finite-state-machine 1 flip-flop 1 flip-flops 1 fsm 1 fulladder 1 next-state-logic 1 ripple-carry-adder 1 seven-segments-display 1 vhdl 1