GitHub topics: flip-flop
thinhNdang536/cos10004-assignment1-digitalstopwatch
⏱️ A step-by-step Logisim Evolution guide for building a digital stopwatch – COS10004 Assignment 1 (2024).
Size: 14.6 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 0 - Forks: 0
mattvenn/flipflop_demo
Flip flop setup, hold & metastability explorer tool
Language: Jupyter Notebook - Size: 34.1 MB - Last synced at: 3 days ago - Pushed at: over 2 years ago - Stars: 34 - Forks: 5
daedalus/bitlogicemu 📦
bitwise operation examples
Language: Python - Size: 15.6 KB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 1
shahriar-raj/CSE_206-Digital-Logic-Design-Sessional
This repository contains all home and lab assignments for the CSE 206: Digital Logic Design Sessional course, part of our Term-1, Level-2 curriculum. It applies theories from CSE 205 to implement digital logics and practically experience them.
Size: 10.2 MB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
dm9gp/flip-flop
Astable Flip-Flop Circuit PCB. View the schematics, inspect or modifiy the circuit, print it.
Size: 1.16 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
AWESOME04/Digital-Systems-Design
This GitHub repository contains coursework projects related to computer systems design. It includes various assignments and projects that cover topics such as digital logic design, computer architecture, and hardware description languages.
Language: VHDL - Size: 3.55 MB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0
nihal-ramaswamy/DDCO-project
A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.
Language: Verilog - Size: 524 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
SimonBuxx/LogiJS
Discover and create logic circuits
Language: JavaScript - Size: 11 MB - Last synced at: 12 months ago - Pushed at: about 2 years ago - Stars: 40 - Forks: 6
NegarMirgati/Latch_and_FF_Analysis
Latch and Flip Flop Analysis Using Hspice
Language: SourcePawn - Size: 1.49 MB - Last synced at: 11 months ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0
FarshidKeivanian/Multi-objective-optimization-of-MOSFETs-channel-widths-and-supply-voltage-in-the-proposed-dual-edge-
FuzzyNSGA-II-Algorithm (Fuzzy adaptive optimisation method)
Language: MATLAB - Size: 1.19 MB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 6 - Forks: 1
JanBurp/MorphaLogic
An eurorack logic module with several logic functions and a clock divider mode. Build around an arduino nano. So could be reprogrammed.
Language: C++ - Size: 7.12 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 0
GSimas/EEL5105
💻 Repositório para Disciplina EEL5105 - Circuitos e Técnicas Digitais - UFSC
Language: VHDL - Size: 271 MB - Last synced at: about 1 year ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 1
GokuGhoul/Embd-iverilog
Embedded Systems Lab Work
Language: Verilog - Size: 24.4 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
imvickykumar999/Logical-Redstone-Reloaded
Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/
Language: Python - Size: 128 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1
hosseinfani/digital_odyssey
Materials for the Computer Science course, Digital Design (Logic Circuits)
Language: C++ - Size: 393 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 4
newajsharif91/Verilog_HDL_Digital-System-Design
CSE-2112 Digital Syatem Design LAb
Language: Verilog - Size: 6.84 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
microchip-pic-avr-examples/avr128db48-blink-led-ccl-mplab-mcc
This MPLAB X Melody code example shows how to make an LED blink using the Configurable Custom Logic (CCL) found in the AVR® DB. The CCL is configured as a toggling J-K flip-flop. The toggling is a result of a timer event.
Language: C - Size: 4.55 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 1
JoelRomero97/Sistemas-Digitales
Implementaciones para diseño de sistemas digitales, comenzando por Flip Flops, registros, autómatas (Máquinas de Moore y Máquinas de Mealy), memorias ROM y sensores de presencia, utilizando para cada uno de estos, distintos contadores (anillo, década, etc).
Language: VHDL - Size: 4.22 MB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 5 - Forks: 1
sedhossein/verilog-bcd-counter-jk-flip-flop
this source is Commercial bcd counter that built with Jk flip-flop in verilog
Language: Verilog - Size: 247 KB - Last synced at: about 2 months ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 0
anthony7586/designing-with-VHDL
porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation
Size: 30.1 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
memgonzales/hdl-flip-flop
Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)
Language: Verilog - Size: 102 KB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
MartinCastroAlvarez/assembly-logisim-circuits
Logic Circuits using Logisim
Language: Assembly - Size: 966 KB - Last synced at: 20 days ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
archy-co/IC_Testers
Testers for some non elementary integrated circuits: Adder 74283, D Flip-Flop 74174 & Counter 74193 written to be run from PSoC 4
Language: C - Size: 77.1 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
Grv-Singh/Digital-Systems-Design
Playing with ⚡ logic gates to make corresponding ✔ decision making circuits solving 🔌 electronic challenges at hand 🚦
Language: MATLAB - Size: 3.24 MB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
