GitHub / sedhossein / verilog-bcd-counter-jk-flip-flop

this source is Commercial bcd counter that built with Jk flip-flop in verilog

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sedhossein%2Fverilog-bcd-counter-jk-flip-flop
PURL: pkg:github/sedhossein/verilog-bcd-counter-jk-flip-flop

Stars: 2
Forks: 0
Open issues: 0

License: None
Language: Verilog
Size: 247 KB
Dependencies parsed at: Pending

Created at: over 7 years ago
Updated at: over 2 years ago
Pushed at: over 7 years ago
Last synced at: 6 months ago

Topics: bcd, counter, flip-flop, logic, verilog

Loading...