GitHub / sedhossein / verilog-bcd-counter-jk-flip-flop
this source is Commercial bcd counter that built with Jk flip-flop in verilog
Stars: 2
Forks: 0
Open issues: 0
License: None
Language: Verilog
Size: 247 KB
Dependencies parsed at: Pending
Created at: almost 7 years ago
Updated at: over 2 years ago
Pushed at: almost 7 years ago
Last synced at: about 2 months ago
Topics: bcd, counter, flip-flop, logic, verilog
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