GitHub topics: digital-design

saadelahii/JTAG-IEEE-1149.1

Basic JTAG standard implementation in Verilog and integration with a CUT

Language: Verilog - Size: 1.01 MB - Last synced at: about 8 hours ago - Pushed at: about 8 hours ago - Stars: 0 - Forks: 0

JuanCantu1/Interactive-Memory-Game

Interactive memory game implemented in Verilog and deployed on Nexys-A7 FPGA using FSM-based logic.

Language: Verilog - Size: 22.6 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 2 - Forks: 0

patsaoglou/JTAG-IEEE-1149.1

Basic JTAG standard implementation in Verilog and integration with a CUT

Language: Verilog - Size: 1 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

alexisvassquez/alexisvassquez

About me

Size: 0 Bytes - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

RadioactiveScandium/Digital-Logic-Design

Digital logic implementation and verification through Verilog/SV

Language: SystemVerilog - Size: 13.9 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1 - Forks: 0

iic-jku/IIC-OSIC-TOOLS Fork of efabless/foss-asic-tools

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Language: Python - Size: 106 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 478 - Forks: 74

ab-ff/Multi-Bit-Comparator

Variations of a multi-bit generalized comparator for different area and timing.

Size: 1000 Bytes - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

shoichiideologies/arduino-based-rfid-door-lock

A Arduino-based door lock system the uses RFID sensor for access control and an LCD display for status monitoring

Language: C++ - Size: 6.84 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

joejo-joestar/uni-codes

🐢

Language: C - Size: 17.4 MB - Last synced at: 10 days ago - Pushed at: 11 days ago - Stars: 2 - Forks: 1

HSD-ESD/VHDL-by-HGB

VHDL-by-HGB is a VS-Code extension for VHDL.

Language: TypeScript - Size: 7.41 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 7 - Forks: 0

player400/pi

My very own CPU architecture! Emulator availible!

Language: C++ - Size: 368 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 5 - Forks: 0

Vaibhav-Gunthe/Verilog-Projects

A collection of Verilog-based digital design projects, from basic gates to complex modules like ALUs, FSMs, and memory units. Ideal for learning RTL design and synthesis.

Language: Verilog - Size: 1020 KB - Last synced at: 15 days ago - Pushed at: 16 days ago - Stars: 3 - Forks: 0

umarnurmatov/harris_excercises

Excersizes from "Digital design and computer architecture"

Language: SystemVerilog - Size: 8.79 KB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 0 - Forks: 0

medwatt/gmid

Python script for generating lookup tables for the gm/ID design methodology and much more ...

Language: Python - Size: 4.8 MB - Last synced at: 23 days ago - Pushed at: 24 days ago - Stars: 81 - Forks: 10

Quanoom/FrequencyDivider

verilog code for frequency divider circuit implemented with verilog hdl

Language: Verilog - Size: 8.79 KB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 1 - Forks: 0

patsaoglou/Built-In-Self-Test

Built-In-Self-Test blocks using LFSRs and MISRs for a circuit under test made in Verilog

Language: Verilog - Size: 439 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

IamMosiow/SPI-Master-VHDL

FSM-based SPI Master implementation in VHDL with simulation and docs

Language: VHDL - Size: 271 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

m-pabon/dlogic

HDL Simulator: Simulate & Verify Your Digital Designs

Language: Rust - Size: 458 KB - Last synced at: 23 days ago - Pushed at: 23 days ago - Stars: 0 - Forks: 0

itzzyashh/sincronizacao-buffer-verilog

Este projeto implementa um sistema modular com comunicação entre diferentes módulos, incluindo um gerador de Fibonacci, um contador de Timer, um controlador baseado em uma máquina de estados, e um módulo wrapper com buffer circular. O sistema é implementado em Verilog e simulado através de um Testbench.

Language: Verilog - Size: 0 Bytes - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

HMarchiori/sincronizacao-buffer-verilog

Este projeto implementa um sistema modular com comunicação entre diferentes módulos, incluindo um gerador de Fibonacci, um contador de Timer, um controlador baseado em uma máquina de estados, e um módulo wrapper com buffer circular. O sistema é implementado em Verilog e simulado através de um Testbench.

Language: Verilog - Size: 19.5 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

HMarchiori/controle-microondas-verilog

Este projeto em Verilog implementa dois módulos principais para controle de um timer, componente de um sistema de microondas. O microondas contém uma máquina de estados finitas, controle lógico para ativação, pausa, e finalização, bem como controle de potência, ativada por meio de controles físicos.

Language: Tcl - Size: 9.77 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

HMarchiori/relogio-xadrez-vhdl

Este projeto implementa um relógio de xadrez utilizando a linguagem VHDL. O sistema gerencia o tempo de jogo de dois jogadores e exibe os tempos restantes em um display.

Language: Tcl - Size: 8.79 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

DrWaleedAYousef/Teaching

Teaching Materials for Dr. Waleed A. Yousef

Language: Mathematica - Size: 157 MB - Last synced at: 30 days ago - Pushed at: 11 months ago - Stars: 1,004 - Forks: 319

baquer/GATE-and-CSE-Resources-for-Students

📚 📖 📚CSE GATE Resources for GATE and CSE Aspirants 😎 😁 . Show your ❤️ by ⭐️⭐️

Size: 225 MB - Last synced at: about 2 months ago - Pushed at: about 1 year ago - Stars: 1,555 - Forks: 411

SKpro-glitch/Multi-Bit-Comparator

Variations of a multi-bit generalized magnitude comparator for different area and timing.

Language: Verilog - Size: 33.2 KB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

HSD-ESD/VUnit-by-HGB

VUnit-by-HGB is a VS-Code extension which enables the testexplorer for VUnit projects.

Language: TypeScript - Size: 1.14 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 3 - Forks: 1

RezaGooner/Logic-circuit-Verilog

Language: Verilog - Size: 5.86 KB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

oguzhansarigol/Digital-Design-Circuits

ESOGU Digital Design(Sayısal Tasarım) Circuits

Size: 69.3 KB - Last synced at: about 1 month ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

meiniKi/FazyRV

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Language: SystemVerilog - Size: 772 KB - Last synced at: about 2 months ago - Pushed at: 8 months ago - Stars: 89 - Forks: 4

chaseruskin/legoHDL

An experimental package manager and development tool for Hardware Description Languages (HDL).

Language: Python - Size: 3.9 MB - Last synced at: 7 days ago - Pushed at: about 3 years ago - Stars: 14 - Forks: 2

SUHANI102003/FSM-BASED-PROJECTS

Mini projects based on Finite State Machines (FSM)

Language: Verilog - Size: 735 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 1

VarshithGovi/Logic_gates

Simulate and analyze fundamental logic gates using Icarus Verilog and GTKWave. This project provides a modular Verilog implementation and a comprehensive testbench for precise validation, offering valuable insights into digital design workflows for VLSI professionals.

Language: Verilog - Size: 33.2 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Ghonimo/Pre_Silicon-AHB-to_APB-Verification

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

Language: SystemVerilog - Size: 13.5 MB - Last synced at: 2 months ago - Pushed at: about 1 year ago - Stars: 22 - Forks: 6

CFZRfrndVolt/Introducing-VHDL-

This repository contains projects and experiments focused on designing, simulating, and implementing digital circuits using VHDL (VHSIC Hardware Description Language) and Quartus II software. The projects covered in this repository serve as an introduction to key concepts in digital system design, including the creation of basic logic circuits, com

Size: 1000 Bytes - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

arasgungore/NandGame

Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.

Size: 4.85 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 14 - Forks: 1

bensampson5/libsv

An open source, parameterized SystemVerilog digital hardware IP library

Language: SystemVerilog - Size: 255 KB - Last synced at: about 8 hours ago - Pushed at: 12 months ago - Stars: 26 - Forks: 4

VarshithGovi/2bit-Ripple-Carry-Adder-Verilog

A Verilog-based implementation of a 2-bit Ripple Carry Adder with a comprehensive testbench for functional verification, ideal for beginners exploring digital design and HDL concepts. 🚀

Language: Verilog - Size: 25.4 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

meiniKi/RV32I_SC_Logisim

A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.

Language: Verilog - Size: 707 KB - Last synced at: about 2 months ago - Pushed at: almost 2 years ago - Stars: 5 - Forks: 0

VarshithGovi/Half-Adder-Design-Verilog

A compact Verilog project implementing a half-adder with gate-level modeling, featuring a detailed testbench for functional verification and simulation.

Language: Verilog - Size: 23.4 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

MohamedHussein27/SPI_Slave_With_Single_Port_Memory

This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with sigle port sync RAM. The project includes the design and code for an SPI Slave, a single-port asynchronous RAM, and an SPI Wrapper that connects the RAM and SPI Slave.

Language: Verilog - Size: 2.18 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 5 - Forks: 0

eonu/fpga

Hardware implementations for basic digital circuit designs in Verilog with a Xilinx Artix-7 FPGA chip on a Digilent Basys 3 development board.

Language: Verilog - Size: 2.03 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Quanoom/SequenceDetector

11001 sequence detector

Language: Verilog - Size: 10.7 KB - Last synced at: 27 days ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

Werni2A/Valhalla-II

Open-Source VHDL Synthesis for Alhambra II FPGA Board

Language: VHDL - Size: 22.5 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 3 - Forks: 2

Abdulrahman-Mostafa10/Synopsys-Chip-Design

Language: Verilog - Size: 8.54 MB - Last synced at: 2 months ago - Pushed at: 5 months ago - Stars: 3 - Forks: 1

aitesam961/16-Bit-RISC-Core-Processor

A RISC custom-ISA, 16-Bit Processor

Language: Verilog - Size: 22.2 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 8 - Forks: 1

defano/digital-design

An introduction to integrated circuit design with Verilog and the Papilio Pro development board.

Language: Verilog - Size: 35.1 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 14 - Forks: 6

dph22/dph22.github.io

online portfolio

Size: 5.69 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

MohamedHussein27/RISC-V-Single-Cycle-Implementation

This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book. The project includes a complete Verilog implementation, supporting various instruction types, with performance enhancements and detailed schematics for analysis.

Language: Verilog - Size: 11.4 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 2 - Forks: 0

anarayandev/Verilog-Projects

Projects using Verilog Language

Size: 970 KB - Last synced at: 8 days ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

tangshi706/tangshi706.github.io Fork of Huxpro/huxpro.github.io

Kenny Blog Web

Language: HTML - Size: 44 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

rx422/CID-Circuit-Tester

CID Circuit Tester is a software tool verifies the accuracy of the obtained logic function simplification and the logic circuit design.

Language: Makefile - Size: 771 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

secure-firmware/ai-hardware-engineer-path

a self-study guide for AI hardware engineers, covering a wide range of topics from foundational knowledge to advanced FPGA and acceleration techniques, Nvidia Jetson and edge AI, and more.

Size: 188 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

quentinlintz/digital-design-labs

🧮 Digital design practice

Language: SystemVerilog - Size: 56.6 KB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

Imtjl/digital-design-fundamentals

Digital design fundamentals - a 3rd year CSE banchelor course in ITMO University

Language: Tcl - Size: 3.14 MB - Last synced at: about 2 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

AnjanaSenanayake/verilog-model-for-8bit-processor

An implementation of a processor with basic components coded in verilog

Language: Verilog - Size: 6.84 KB - Last synced at: 2 months ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 2

arasgungore/256-colors-with-VGA

A VHDL-based VGA driver to display 256 different colors on a monitor.

Language: VHDL - Size: 492 KB - Last synced at: about 2 months ago - Pushed at: almost 3 years ago - Stars: 14 - Forks: 0

thomaslaner/academicProjects

A portfolio of technical projects completed during my studies at the Technical University of Vienna, covering areas like digital design, data analytics, embedded systems, and enterprise architecture.

Language: Jupyter Notebook - Size: 38.3 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

aditeyabaral/DDCO-Lab-UE18CS207

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

Language: Verilog - Size: 1.82 MB - Last synced at: 2 months ago - Pushed at: about 5 years ago - Stars: 16 - Forks: 9

Mostafa-wael/SPI-Protocol

A digital design for the SPI protocol, delivered as a project for the logic design course

Language: Verilog - Size: 2.51 MB - Last synced at: about 2 months ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 2

flavian112/ethz_ddca

Digital Design and Computer Architecture, SAFARI ETHZ Course Notes.

Language: Verilog - Size: 59.8 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

LunaQu4kez/CS207_23F_Project_GenshinKitchen

2023 Fall CS207 Digital Design Course Project with 120/100 (Full Score)

Language: VHDL - Size: 88.6 MB - Last synced at: 6 months ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 0

Moataz-mohsen/traffic-controller-

traffic light controller

Language: VHDL - Size: 9.77 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

Jeremy-434/helloDesign

A platform for companies to contract graphic design services on a monthly subscription basis. Users can define design tasks, such as logos and banners, and communicate with designers through an integrated chat, all with minimal need for direct interaction and maximum automation of the process.

Language: TypeScript - Size: 60.5 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

shahed22/verilog-module-generator-for-state-machine

A Python-based tool for generating Verilog modules with features including customizable state machines, port definitions, and state diagrams using Graphviz. Ideal for FPGA and ASIC design workflows.

Language: Python - Size: 40 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

aditeyabaral/up-down-counter

A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.

Language: Verilog - Size: 10.7 KB - Last synced at: 2 months ago - Pushed at: about 5 years ago - Stars: 4 - Forks: 2

ivanvig/cordicio

Chisel implementation of a CORDIC design

Language: Scala - Size: 70.3 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

kara-abdelaziz/SEP-CPU

SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU

Language: Assembly - Size: 201 KB - Last synced at: 10 months ago - Pushed at: over 3 years ago - Stars: 5 - Forks: 1

kara-abdelaziz/Simple-VGA-card

A hardware implementation on Logisim of the World's Worst Video Card designed by Ben Eater.

Language: TeX - Size: 476 KB - Last synced at: 10 months ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

rishz09/digital-safe-verilog

A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board

Language: Tcl - Size: 2.06 MB - Last synced at: 3 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

taddeo123/Adobe-Dimension-repack

adobe-dimension-download, adobe-dimension-2024-free, adobe-dimension-installer, download-adobe-dimension-free, get-adobe-dimension-2024, how-to-download-adobe-dimension, adobe-dimension-activation-free, free-adobe-dimension-download, digital-design, digital-creation, graphic-design-tools, adobe-software-download, adobe-dimension-tools, adobe-dimens

Language: C++ - Size: 40 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

thedatabusdotio/fpga-ml-accelerator

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

Language: Verilog - Size: 21.5 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 103 - Forks: 23

eshansurendra/UART-FPGA

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.

Language: SystemVerilog - Size: 3.5 MB - Last synced at: 2 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

Omarmuhammadmu/FFE_digital_implementation

The implementation of a FFE using only one adder and one multiplier. Specifications include a 1 MHz input data frequency and a 4 MHz FFE clock frequency, with the output being a 12-bit signed value available every 4 FFE clock cycles. The paper details the design, provides pseudo code, Verilog code, the Verilog netlist, and suggests optimizations.

Language: Verilog - Size: 525 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0