GitHub / rishz09 / digital-safe-verilog
A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rishz09%2Fdigital-safe-verilog
Stars: 0
Forks: 0
Open issues: 0
License: None
Language: Tcl
Size: 2.06 MB
Dependencies parsed at: Pending
Created at: 11 months ago
Updated at: 11 months ago
Pushed at: 11 months ago
Last synced at: 3 months ago
Topics: digital-design, digital-safe, pynq-z2, verilog, verilog-project, vivado, vivado-simulator
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