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GitHub topics: vivado-simulator

TahirZia-1/UART-Transmitter-and-Receiver

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

Language: SystemVerilog - Size: 231 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

TahirZia-1/Digital-Clock-Verilog

This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.

Language: Tcl - Size: 166 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

wyvernSemi/mem_model

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Language: VHDL - Size: 2.71 MB - Last synced at: 24 days ago - Pushed at: 5 months ago - Stars: 22 - Forks: 3

bp0609/Mini-Processor-Verilog-FPGA-Implemented

This repo contains a mini-processor design implemented on FPGA using verilog

Language: Verilog - Size: 1.28 MB - Last synced at: 2 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

Imtjl/digital-design-fundamentals

Digital design fundamentals - a 3rd year CSE banchelor course in ITMO University

Language: Tcl - Size: 3.14 MB - Last synced at: about 1 month ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

anr2311/I2C_State_Machine

This repo contains an I2C transaction state machine modelled in Verilog targeted for the Zynq Zedboard

Language: Verilog - Size: 0 Bytes - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

suoto/hdl_checker

Repurposing existing HDL tools to help writing better code

Language: Python - Size: 1.05 MB - Last synced at: 5 months ago - Pushed at: 11 months ago - Stars: 192 - Forks: 22

amirah-sri/all_verilog

I am trying to develop my skills through daily practice and consistency.

Language: Verilog - Size: 735 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

rishz09/digital-safe-verilog

A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board

Language: Tcl - Size: 2.06 MB - Last synced at: 2 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/SystemVerilog_Practice

Practice Codes of SystemVerilog Language

Language: SystemVerilog - Size: 48.8 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

arhamhashmi01/Axi4-lite

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

Language: SystemVerilog - Size: 390 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

mzh330521/SublimeLinter-contrib-xsim

Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.

Language: Python - Size: 18.6 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 8 - Forks: 2

Arjun-Narula/Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

Language: JavaScript - Size: 2.07 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 29 - Forks: 7

RipperJ/VerilogExpr2NAND-NOR

Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation

Language: Python - Size: 42 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

esynr3z/pyhdlsim

Example of Python and PyTest powered workflow for a HDL simulation

Language: Python - Size: 11.7 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 9 - Forks: 1