GitHub topics: axi4-protocol

Repositories

dpretet/axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

Language: SystemVerilog - Size: 364 KB - Last synced at: 3 days ago - Pushed at: 23 days ago - Stars: 156 - Forks: 29

yunusesergun/yesergun.fpga.dev

All about FPGA...

Language: Tcl - Size: 2.24 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 0

muhammadtalhasami/Axi4_lite_interface

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

Language: SystemVerilog - Size: 104 KB - Last synced at: 26 days ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 1

arhamhashmi01/Axi4-lite

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

Language: SystemVerilog - Size: 390 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

dpretet/friscv

RISCV CPU implementation in SystemVerilog

Language: Coq - Size: 4.1 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 15 - Forks: 4

CSpyridakis/Reconfigurable-Computing 📦

Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)

Language: C++ - Size: 114 MB - Last synced at: 7 days ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 2

Related Keywords

axi4-protocol 6 axi4 4 axi4-lite 4 fpga 4 vivado 3 verilog 3 systemverilog 2 verilator 2 axi4-lite-interface 2 vhdl 2 riscv 2 fpga-soc 2 asic 2 crossbar 2 asic-design 2 zynq-7000 1 vivado-simulator 1 zynq 1 assembler 1 risc-v 1 xilinx 1 riscv-cpu 1 rv32i 1 axi4-stream-protocol 1 evaluation-board 1 hls 1 reconfigurable-computing 1 rsoc 1 vivado-hls 1 hardware-designs 1 system-verilog 1 axi4-lite-system-verilog 1 rtl 1 clock 1 soc 1 riscv64 1 riscv32 1 processor 1 monodraw 1 interconnect 1 axi4-full 1 arm 1 amba 1

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