Ecosyste.ms: Repos
An open API service providing repository metadata for many open source software ecosystems.
GitHub topics: axi4
Functional-Bus-Description-Language/go-fbdl
Functional Bus Description Language compiler front-end written in Go.
Language: Go - Size: 1.3 MB - Last synced: 2 days ago - Pushed: 2 days ago - Stars: 0 - Forks: 1
OSVVM/AXI4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
Language: VHDL - Size: 2.48 MB - Last synced: 8 days ago - Pushed: 9 days ago - Stars: 104 - Forks: 15
dpretet/axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
Language: SystemVerilog - Size: 296 KB - Last synced: 8 days ago - Pushed: 9 days ago - Stars: 91 - Forks: 23
chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
Language: SystemVerilog - Size: 46 MB - Last synced: 16 days ago - Pushed: 23 days ago - Stars: 223 - Forks: 65
pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Language: SystemVerilog - Size: 8.04 MB - Last synced: 15 days ago - Pushed: 15 days ago - Stars: 943 - Forks: 241
signature-ip-ai/amba-tlm
AMBA TLM Library
Language: C++ - Size: 1.03 MB - Last synced: 21 days ago - Pushed: 21 days ago - Stars: 0 - Forks: 0
rggen/rggen-sv-rtl
Common SystemVerilog RTL modules for RgGen
Language: SystemVerilog - Size: 92.8 KB - Last synced: 22 days ago - Pushed: 22 days ago - Stars: 11 - Forks: 3
taichi-ishitani/tvip-axi
AMBA AXI VIP
Language: SystemVerilog - Size: 147 KB - Last synced: 24 days ago - Pushed: 24 days ago - Stars: 300 - Forks: 94
muhammadtalhasami/Axi4_lite_interface
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
Language: SystemVerilog - Size: 104 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 1
dpretet/friscv
RISCV CPU implementation in SystemVerilog
Language: Coq - Size: 4.1 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 15 - Forks: 3
ultraembedded/core_dvi_framebuffer
Minimal DVI / HDMI Framebuffer
Language: Verilog - Size: 77.1 KB - Last synced: about 1 month ago - Pushed: almost 4 years ago - Stars: 69 - Forks: 10
taichi-ishitani/tnoc
Network on Chip Implementation written in SytemVerilog
Language: SystemVerilog - Size: 406 KB - Last synced: about 1 month ago - Pushed: almost 2 years ago - Stars: 133 - Forks: 40
ultraembedded/core_dbg_bridge
UART -> AXI Bridge
Language: Verilog - Size: 21.5 KB - Last synced: about 1 month ago - Pushed: almost 3 years ago - Stars: 45 - Forks: 16
ultraembedded/core_ft60x_axi
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
Language: C++ - Size: 4.29 MB - Last synced: about 1 month ago - Pushed: about 4 years ago - Stars: 77 - Forks: 25
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
Language: SystemVerilog - Size: 17.6 MB - Last synced: about 2 months ago - Pushed: about 1 year ago - Stars: 771 - Forks: 205
Ammar-Bin-Amir/AXI4
RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
Language: Verilog - Size: 19.5 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 0 - Forks: 0
ultraembedded/core_sdram_axi4
SDRAM controller with AXI4 interface
Language: C++ - Size: 43 KB - Last synced: about 1 month ago - Pushed: almost 5 years ago - Stars: 64 - Forks: 26
dpretet/meduram
Multi-port BRAM IP for ASIC and FPGA
Language: SystemVerilog - Size: 241 KB - Last synced: about 1 month ago - Pushed: about 3 years ago - Stars: 10 - Forks: 2
ultraembedded/core_ftdi_bridge
FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
Language: Verilog - Size: 19.5 KB - Last synced: about 1 month ago - Pushed: about 3 years ago - Stars: 23 - Forks: 9
aignacio/ravenoc
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
Language: SystemVerilog - Size: 2.27 MB - Last synced: 3 months ago - Pushed: 12 months ago - Stars: 119 - Forks: 25
WangXuan95/FPGA-DDR-SDRAM
An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。
Language: Verilog - Size: 437 KB - Last synced: 3 months ago - Pushed: 9 months ago - Stars: 106 - Forks: 21
oscc-ip/sdram
An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.
Language: Makefile - Size: 445 KB - Last synced: 9 days ago - Pushed: 9 days ago - Stars: 7 - Forks: 1
ultraembedded/core_spiflash
SPI-Flash XIP Interface (Verilog)
Language: Verilog - Size: 23.4 KB - Last synced: about 1 month ago - Pushed: over 2 years ago - Stars: 34 - Forks: 11
ultraembedded/cortex_m0_wrapper
Cortex-M0 DesignStart Wrapper
Language: C++ - Size: 52.7 KB - Last synced: about 1 month ago - Pushed: almost 5 years ago - Stars: 17 - Forks: 7
Hanley-Yao/Zynq7010_eink_controller
这是一个基于Zynq7010的Eink控制器 在ED097TC2上高质量显示帧数高达10FPS
Language: C - Size: 475 MB - Last synced: 7 months ago - Pushed: 10 months ago - Stars: 165 - Forks: 21
ic-lab-duth/NoCpad
HLS for Networks-on-Chip
Language: C++ - Size: 339 KB - Last synced: 8 months ago - Pushed: over 3 years ago - Stars: 22 - Forks: 4
yohanes-erwin/zynq7000
[Course] Hands-On ZYNQ: Mastering AXI4 Bus Protocol
Language: Verilog - Size: 23.4 KB - Last synced: 8 months ago - Pushed: over 4 years ago - Stars: 9 - Forks: 7
gednyengs/dma
Open-Source AXI4 DMA Engine in SystemVerilog and Chisel
Language: Scala - Size: 4.46 MB - Last synced: 10 months ago - Pushed: about 2 years ago - Stars: 4 - Forks: 3
mnemocron/axi-perf-counter-pattern
Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.
Language: VHDL - Size: 856 KB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0
loykylewong/FPGA-Application-Development-and-Simulation
《FPGA应用开发和仿真》(机械工业出版社2018年第1版 ISBN:9787111582786)的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
Language: SystemVerilog - Size: 8.37 MB - Last synced: 11 months ago - Pushed: 11 months ago - Stars: 96 - Forks: 25
CSpyridakis/Reconfigurable-Computing 📦
Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
Language: C++ - Size: 114 MB - Last synced: 10 months ago - Pushed: over 3 years ago - Stars: 3 - Forks: 2
xunqianxun/liguoqi-rv64-cpu
RISC-V 64 CPU
Language: C++ - Size: 57.6 MB - Last synced: 12 months ago - Pushed: over 1 year ago - Stars: 5 - Forks: 2
amamory/axis-protocol-checker
AXI stream protocol checking design
Language: Tcl - Size: 86.9 KB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 2 - Forks: 0
amamory/axis_s_led_ip
A Vivado IP to connect LEDs to a slave AXI streaming interface
Language: Tcl - Size: 19.5 KB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 2 - Forks: 0
airhdl/spi-to-axi-bridge
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
Language: VHDL - Size: 151 KB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 20 - Forks: 4
mmxsrup/axi4-interface
AXI4 and AXI4-Lite interface definitions
Language: SystemVerilog - Size: 31.3 KB - Last synced: over 1 year ago - Pushed: over 3 years ago - Stars: 41 - Forks: 19
sarthi92/boron_codesign
ZYNQ7 FPGA Co-design of BORON Cipher
Language: Verilog - Size: 42 KB - Last synced: over 1 year ago - Pushed: over 5 years ago - Stars: 2 - Forks: 1
gururavi/rtl
Synchronous and Asynchronous FIFO with AXI interface
Language: SystemVerilog - Size: 9.77 KB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 1 - Forks: 0
Lampro-Mellon/Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
Language: Scala - Size: 155 MB - Last synced: over 1 year ago - Pushed: about 3 years ago - Stars: 23 - Forks: 8
nhynes/chisel3-axi
Chisel3 AXI4-{Lite, Full, Stream} Definitions
Language: Scala - Size: 15.6 KB - Last synced: 10 months ago - Pushed: over 5 years ago - Stars: 11 - Forks: 4
amamory/axi_noc_counter_ip
A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source
Language: Tcl - Size: 32.2 KB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 1 - Forks: 0
amamory/axis_m_dip_ip
A Vivado IP to connect dip switches to a master AXI streaming interface
Language: Tcl - Size: 25.4 KB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 1 - Forks: 0
amamory/axis_m_const_ip
Constant value for an AXI master streaming interface
Language: Tcl - Size: 42 KB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 1 - Forks: 1
amamory/zynq-ps-hermes-noc
Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface
Language: Tcl - Size: 990 KB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 1 - Forks: 0
amamory/zynq-hermes-noc-demo
A demonstrator of Hermes network-on-chip communicating with the ARM processor
Language: Tcl - Size: 74.2 KB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 1 - Forks: 2
rlee287/hardware-bus-infrastructure
A collection of formal properties for hardware buses, and cores using them.
Language: Verilog - Size: 78.1 KB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 2 - Forks: 0
ShanghaitechGeekPie/chisel3-typed-axi4
A group of typed definition of AXI4 in Chisel3.
Language: Scala - Size: 20.5 KB - Last synced: over 1 year ago - Pushed: almost 5 years ago - Stars: 4 - Forks: 0