GitHub / oscc-ip / sdram
An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/oscc-ip%2Fsdram
PURL: pkg:github/oscc-ip/sdram
Stars: 17
Forks: 2
Open issues: 1
License: None
Language: Scala
Size: 2.11 MB
Dependencies parsed at: Pending
Created at: almost 2 years ago
Updated at: 3 months ago
Pushed at: 2 months ago
Last synced at: 2 months ago
Topics: axi4, fpga, sdram, tapeout, verilog
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