kivikakk/ili9341spi

Sketching out an ILI9341 SPI driver, with a Zig testbench

Language: Zig - Size: 1.84 MB - Last synced: about 8 hours ago - Pushed: about 15 hours ago - Stars: 0 - Forks: 0

chryse-hdl/chryse

Project framework for Chisel

Language: Scala - Size: 301 KB - Last synced: about 7 hours ago - Pushed: about 15 hours ago - Stars: 2 - Forks: 0

atrosinenko/simpleinst

Make writing trivial inst{ruction,rumentation}s for RocketChip as simple as writing the C code

Language: Scala - Size: 16.6 KB - Last synced: about 17 hours ago - Pushed: almost 5 years ago - Stars: 4 - Forks: 1

FyraLabs/chisel-operator

Kubernetes Operator for Chisel

Language: Rust - Size: 571 KB - Last synced: 1 day ago - Pushed: 2 days ago - Stars: 68 - Forks: 7

Lickton/npc

Language: Scala - Size: 81.1 KB - Last synced: 3 days ago - Pushed: 3 days ago - Stars: 1 - Forks: 0

chiselverify/chiselverify

A dynamic verification library for Chisel.

Language: Scala - Size: 5.11 MB - Last synced: 5 days ago - Pushed: 6 days ago - Stars: 134 - Forks: 21

NextChapterSoftware/chissl

A tool to create HTTPS reverse tunnels

Language: Go - Size: 227 KB - Last synced: 5 days ago - Pushed: 6 days ago - Stars: 11 - Forks: 0

ucb-bar/riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

Language: Scala - Size: 1.3 MB - Last synced: 9 days ago - Pushed: 9 days ago - Stars: 507 - Forks: 102

chryse-hdl/chryse-template

Template to start using Chryse

Language: Scala - Size: 33.2 KB - Last synced: 11 days ago - Pushed: 12 days ago - Stars: 0 - Forks: 0

peacefulotter/Mintel

A 5-stage pipelined RISC microprocessor written in Scala using Chisel

Language: Verilog - Size: 489 KB - Last synced: 12 days ago - Pushed: about 2 years ago - Stars: 1 - Forks: 0

chipsalliance/rocket-chip

Rocket Chip Generator

Language: Scala - Size: 20.1 MB - Last synced: 22 days ago - Pushed: 22 days ago - Stars: 3,031 - Forks: 1,072

yfzcsc/fpga_final_project

An NPU by chisel 3.4.3.

Language: Scala - Size: 759 KB - Last synced: 13 days ago - Pushed: over 2 years ago - Stars: 4 - Forks: 0

firesim/icenet

Network components (NIC, Switch) for FireBox

Language: Scala - Size: 301 KB - Last synced: 14 days ago - Pushed: 15 days ago - Stars: 15 - Forks: 20

riscv-boom/riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

Language: Scala - Size: 12.1 MB - Last synced: 25 days ago - Pushed: 26 days ago - Stars: 1,609 - Forks: 401

yasnakateb/CGRAs

Coarse Grained Reconfigurable Arrays with Chisel3

Language: Scala - Size: 3.03 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 11 - Forks: 0

ucb-bar/chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Language: Scala - Size: 49.9 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 1,430 - Forks: 587

RadicalCSG/Chisel.Prototype

Work in progress prototype for the Chisel Level Editor, for Unity

Language: C# - Size: 12 MB - Last synced: about 1 month ago - Pushed: about 2 years ago - Stars: 459 - Forks: 33

Chisel-blocks/asyncfifo

Asynchronous FIFO for clock domain crossing. Written in Chisel. Re-used from https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/util/AsyncQueue.scala

Language: Scala - Size: 28.3 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

ovh/sv2chisel

(System)Verilog to Chisel translator

Language: Scala - Size: 492 KB - Last synced: about 1 month ago - Pushed: about 2 years ago - Stars: 97 - Forks: 10

ucb-bar/chiseltest

The batteries-included testing and formal verification library for Chisel-based RTL designs.

Language: Scala - Size: 1.4 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 198 - Forks: 69

ucb-bar/constellation

A Chisel RTL generator for network-on-chip interconnects

Language: Scala - Size: 1.59 MB - Last synced: about 2 months ago - Pushed: 4 months ago - Stars: 143 - Forks: 21

ka-el-thas/chips-el

chisel helper to reverse tunnel between two main and client server

Language: Python - Size: 6.84 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

rameloni/Tydi-Chisel-testing-frameworks-analysis

An analysis of available testing frameworks for Tydi-Chisel

Size: 18.2 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

Sonra0/Config-server

Tools to optimize your linux server and config your vpn tunnel

Language: Python - Size: 165 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 2 - Forks: 0

chipsalliance/chisel

Chisel: A Modern Hardware Design Language

Language: Scala - Size: 93.7 MB - Last synced: about 2 months ago - Pushed: 2 months ago - Stars: 3,695 - Forks: 568

OpenXiangShan/XiangShan

Open-source high-performance RISC-V processor

Language: Scala - Size: 70.7 MB - Last synced: about 2 months ago - Pushed: 2 months ago - Stars: 4,293 - Forks: 594

cxnturi0n/pivoting-tunneling-lab

Compromise a web application and delve deeper into the network to access hosts that you cannot directly reach from your attack host using different approaches.

Language: JavaScript - Size: 17.3 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 1 - Forks: 0

envato-archive/chisel-scripts 📦

Chisel scripts created to debug any issues

Language: Lua - Size: 4.88 KB - Last synced: about 2 months ago - Pushed: over 2 years ago - Stars: 2 - Forks: 0

rhysd/riscv32-cpu-chisel

Learning how to make RISC-V 32bit CPU with Chisel

Language: Scala - Size: 143 KB - Last synced: about 2 months ago - Pushed: over 2 years ago - Stars: 50 - Forks: 3

carlosedp/chiselv

A RISC-V Core (RV32I) written in Chisel HDL

Language: Scala - Size: 465 KB - Last synced: about 2 months ago - Pushed: 5 months ago - Stars: 92 - Forks: 17

t3l3machus/pentest-pivoting

A compact guide to network pivoting for penetration testings / CTF challenges.

Size: 52.7 KB - Last synced: about 1 month ago - Pushed: over 1 year ago - Stars: 166 - Forks: 40

thoughtworks/hardposit-chisel3

Chisel library for Unum Type-III Posit Arithmetic

Language: Scala - Size: 4.31 MB - Last synced: about 2 months ago - Pushed: 2 months ago - Stars: 28 - Forks: 7

ucsc-vama/essent

high-performance RTL simulator

Language: Scala - Size: 967 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 105 - Forks: 11

im-tomu/fomu-workshop

Support files for participating in a Fomu workshop

Language: Verilog - Size: 26.4 MB - Last synced: about 1 month ago - Pushed: 3 months ago - Stars: 156 - Forks: 63

Groupsun/riscv-mini-five-stage

This is my graduation project, a simple processor soft core, which implements RV32I ISA.

Language: Scala - Size: 768 KB - Last synced: 3 months ago - Pushed: about 5 years ago - Stars: 6 - Forks: 1

alanjian85/trinity

A rasterization-based GPU created for real-time rendering

Language: C++ - Size: 30.2 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 5 - Forks: 2

bu-icsg/dana

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

Language: Scala - Size: 1.81 MB - Last synced: 2 months ago - Pushed: over 4 years ago - Stars: 203 - Forks: 36

IBM/chiffre

A fault-injection framework using Chisel and FIRRTL

Language: Scala - Size: 11.1 MB - Last synced: 2 months ago - Pushed: over 1 year ago - Stars: 28 - Forks: 14

merledu/magma-si

Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL

Language: Scala - Size: 46.8 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 8 - Forks: 3

michaelmortensen-m4y/Michael_RISC-V_Chisel

RISC-V 1 and 5-stage CPUs Described in Chisel for Implementation in an Altera FPGA

Language: Scala - Size: 3.03 MB - Last synced: 3 months ago - Pushed: over 6 years ago - Stars: 1 - Forks: 0

carlosedp/chisel-template

Chisel HDL Template Repository

Language: Scala - Size: 52.7 KB - Last synced: about 2 months ago - Pushed: over 1 year ago - Stars: 5 - Forks: 2

mgnfy-view/foundry-ethernaut

Porting all Ethernaut challenges to Foundry

Language: Solidity - Size: 31.3 KB - Last synced: 14 days ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

CMU-SAFARI/Pythia-HDL

Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, please read the paper that appeared in MICRO 2021 by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

Language: Scala - Size: 753 KB - Last synced: about 2 months ago - Pushed: over 2 years ago - Stars: 11 - Forks: 3

m3rcer/Chisel-Strike

A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.

Language: C# - Size: 73.1 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 421 - Forks: 57

opiran-club/pf-tun

All-in-one OPIran scripts

Language: Shell - Size: 127 KB - Last synced: 3 months ago - Pushed: 4 months ago - Stars: 47 - Forks: 14

lfiolhais/vim-chisel

Vim syntax highlight for Chisel

Language: Vim script - Size: 17.6 KB - Last synced: about 2 months ago - Pushed: about 3 years ago - Stars: 6 - Forks: 1

freechipsproject/diagrammer

Provides dot visualizations of chisel/firrtl circuits

Language: Scala - Size: 270 KB - Last synced: 4 months ago - Pushed: about 1 year ago - Stars: 106 - Forks: 20

sifive/chisel-circt 📦

Library to compile Chisel circuits using LLVM/MLIR (CIRCT)

Language: Scala - Size: 103 KB - Last synced: about 2 months ago - Pushed: over 1 year ago - Stars: 68 - Forks: 9

Azumi67/Direct_Chisel

Establishing a Direct tunnel using chisel between Servers and Client - IPV4 | IPV6 - TCP | UDP - [5] Kharej [1] IRAN

Language: Python - Size: 209 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 44 - Forks: 11

RPTU-EIS/ADSProject

This repository contains the basic files for the class project of the course "Architecture of Digital Systems I"

Language: Scala - Size: 1.37 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 1 - Forks: 2

CricySaray/Chisel-Bootcamp-Practice

The practice of learning the Chisel bootcamp from GitHub repo whose website is below:

Language: Jupyter Notebook - Size: 2.05 MB - Last synced: 4 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

Lawrence-Leung/olympusV

A curriculum design of computer architecture course, maintained by a group of five innovative and creative students.

Language: Verilog - Size: 6.62 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 1

ubuntu-rocks/.github

The Rocks Community profile and public information

Size: 93.8 KB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

MrAMS/hello_chisel

A Chisel Template with VERILATOR and NVBoard

Language: Scala - Size: 13.7 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

Azumi67/Chisel_multipleServers

Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.

Language: Python - Size: 206 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 11 - Forks: 4

zeeshanrafique23/RV32I-Chisel

This repo contains the files of the RV32I Single-cycle processor in CHISEL.

Language: XSLT - Size: 1.04 MB - Last synced: 6 months ago - Pushed: over 4 years ago - Stars: 1 - Forks: 0

UCTECHIP/rocket_chip_vpu

Language: Scala - Size: 205 KB - Last synced: 3 months ago - Pushed: over 3 years ago - Stars: 8 - Forks: 6

IBM/perfect-chisel

Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program

Language: Scala - Size: 26.4 KB - Last synced: 2 months ago - Pushed: over 1 year ago - Stars: 28 - Forks: 15

AnimMouse/SOCKS5-Proxy-Codespaces

SOCKS5 proxy running on GitHub Codespaces using Chisel

Size: 10.7 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 9 - Forks: 3

grebe/ofdm

Chisel Things for OFDM

Language: Scala - Size: 79.4 MB - Last synced: about 2 months ago - Pushed: almost 4 years ago - Stars: 28 - Forks: 7

microdynamics-cpu/tree-core-cpu

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Language: Scala - Size: 658 KB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 29 - Forks: 2

merledu/100DaysOfCHISEL

100 Days of CHISEL inspired by 100DaysOfRTL

Language: Scala - Size: 1.46 MB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 8 - Forks: 16

bathtub-01/cluster-AES

Optimized Chisel implementations for AES and SM4.

Language: Scala - Size: 173 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

opensocsysarch/CoreGen

OpenSoC System Architect CoreGen Library Infrastructure

Language: C++ - Size: 46 MB - Last synced: 8 months ago - Pushed: over 1 year ago - Stars: 9 - Forks: 2

MaxXSoft/Frenda

Split large FIRRTL into separated modules for incremental compilation.

Language: Scala - Size: 113 KB - Last synced: 8 months ago - Pushed: over 2 years ago - Stars: 8 - Forks: 1

MaxXSoft/Bossa

BOOM's Simulation Accelerator.

Language: Scala - Size: 104 KB - Last synced: 8 months ago - Pushed: over 2 years ago - Stars: 9 - Forks: 1

esperantotech/boom-template Fork of ucb-bar/chipyard

A template for building new projects/platforms using the BOOM core.

Language: Shell - Size: 149 KB - Last synced: 5 months ago - Pushed: over 5 years ago - Stars: 24 - Forks: 20

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Language: VHDL - Size: 46.9 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 2 - Forks: 1

madsrumlenordstrom/chisel-f4pga-flow

Open source flow for generating bitstreams from Chisel code

Language: Makefile - Size: 31.3 KB - Last synced: 5 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

ParkDongho/PolyNetFPGA

DNN Accelerator Generator for FPGA

Language: Scala - Size: 296 KB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 1 - Forks: 0

wangrunji0408/rjrouter

[AFK] Hardware router in Chisel (THU Network Joint Lab 2020)

Language: Scala - Size: 72.3 KB - Last synced: 3 months ago - Pushed: over 3 years ago - Stars: 14 - Forks: 0

IT302/cdl

Chisel Designer's Library

Language: Scala - Size: 20.5 KB - Last synced: 3 months ago - Pushed: over 7 years ago - Stars: 1 - Forks: 1

sifive/chisel-circt-demo

Demonstration of a project using sifive/chisel-circt

Language: Scala - Size: 20.5 KB - Last synced: about 2 months ago - Pushed: over 1 year ago - Stars: 9 - Forks: 1

maltanar/fpga-tidbits

Chisel components for FPGA projects

Language: Verilog - Size: 822 KB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 99 - Forks: 26

connormas/MultiScalarMultiplication

Chisel module for performing Multi-Scalar Multiplication

Language: Scala - Size: 711 KB - Last synced: 8 months ago - Pushed: about 2 years ago - Stars: 10 - Forks: 3

gednyengs/dma

Open-Source AXI4 DMA Engine in SystemVerilog and Chisel

Language: Scala - Size: 4.46 MB - Last synced: 10 months ago - Pushed: over 2 years ago - Stars: 4 - Forks: 3

ltfschoen/MUDTemplate

Build Ethereum DApps with MUD v2 in a Docker container

Language: Shell - Size: 154 KB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 3 - Forks: 0

Bindless-Chicken/chisel-blinky

Boilerplate for a full project with chisel and a DE0 Nano

Language: Scala - Size: 7.81 KB - Last synced: 10 months ago - Pushed: over 4 years ago - Stars: 0 - Forks: 0

buhe/study_fpga

💾 fpga study with open source tools (on macos)

Language: Scala - Size: 3.31 MB - Last synced: 10 months ago - Pushed: about 2 years ago - Stars: 2 - Forks: 0

carlosedp/chisel-bleep-template

A Chisel HDL template using Scala Bleep build tool

Language: Scala - Size: 4.88 KB - Last synced: about 2 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0

AhsanAliUet/Ahsan-Ali-Interests

My interests and some collaborations

Size: 2.93 KB - Last synced: 11 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

inkydragon/chisel-book-cn Fork of redpanda3/chisel-book

<Digital Design with Chisel> 中译版 <Chisel 数字电路设计>

Language: TeX - Size: 13.3 MB - Last synced: 11 months ago - Pushed: 11 months ago - Stars: 0 - Forks: 0

SingularityKChen/langchain-vlsi-flow

LangChain based VLSI flow that is able to generate required HDL, testbench, design creation and implementaion scripts.

Language: Makefile - Size: 355 KB - Last synced: 11 months ago - Pushed: 11 months ago - Stars: 1 - Forks: 0

apavanello/chisel-web-proxy

A Chisel Web Proxy Interface using Vue, Go (golang), gRPC and gRPC-WEB

Language: JavaScript - Size: 326 KB - Last synced: 11 months ago - Pushed: about 2 years ago - Stars: 3 - Forks: 1

IA-C-Lab-Fudan/Chisel-FFT-generator

FFT generator using Chisel

Language: Verilog - Size: 804 KB - Last synced: 10 months ago - Pushed: over 2 years ago - Stars: 37 - Forks: 15

astrohan/romi

ROMI(RISC-V Open Microprocessor Initiative)

Language: Scala - Size: 73.2 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

hplp/aes_chisel

Implementation of the Advanced Encryption Standard in Chisel

Language: Scala - Size: 579 KB - Last synced: 12 months ago - Pushed: about 2 years ago - Stars: 18 - Forks: 2

sammck-go/wstunnel

wstunnel provides extensible, secure TCP tunneling through an HTTP/websocket server

Language: Go - Size: 6.36 MB - Last synced: 11 months ago - Pushed: about 3 years ago - Stars: 2 - Forks: 2

Tomatotech90/DropperChisel

easy chisel dropper

Language: Shell - Size: 16.6 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

Starrynightzyq/soNN

A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.

Language: Verilog - Size: 12.6 MB - Last synced: about 1 year ago - Pushed: almost 3 years ago - Stars: 18 - Forks: 5

VitalyAnkh/open-fpga-tutorial

Open FPGA Tutorial

Language: Verilog - Size: 32.1 MB - Last synced: 26 days ago - Pushed: about 1 year ago - Stars: 1 - Forks: 0

chiselverify/documentation

Documentation surrounding the ChiselVerify project. This includes presentations and research papers written on the topic.

Language: TeX - Size: 18.8 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 5 - Forks: 2

citrus-lemon/riscv-self

mini risc-v kernel by Chisel 3

Language: Scala - Size: 40 KB - Last synced: about 1 year ago - Pushed: almost 3 years ago - Stars: 8 - Forks: 2

just1689/chisel-helm

The unofficial Helm Chart for jpillora's Chisel

Language: Smarty - Size: 32.2 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 3 - Forks: 1

sergiovks/eCPPTv2-Personal-Cheatsheet-ESP-

Personal CheatSheet used for the exam made with Obsidian, download the repo and use the resources within Obsidian for a better experience. CHISEL & SOCAT BINARIES ARE WITHIN THE PIVOTING SECTION.

Size: 12 MB - Last synced: over 1 year ago - Pushed: over 1 year ago - Stars: 16 - Forks: 2

Haouo/vriscv-cpu

5 Stage Pipeline CPU base on RV32I with a few V-Extension Support

Language: Scala - Size: 896 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

pku-liang/Sanger Fork of hatsu3/Sanger

A co-design architecture on sparse attention

Size: 92.8 KB - Last synced: over 1 year ago - Pushed: almost 3 years ago - Stars: 15 - Forks: 3

MaxXSoft/Fuxi

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

Language: Verilog - Size: 1.65 MB - Last synced: over 1 year ago - Pushed: almost 3 years ago - Stars: 93 - Forks: 17

panda5mt/KyogenRV

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Language: Scala - Size: 19.6 MB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 39 - Forks: 3

sujinnaljin/Improving_Productivity

🛠 lldb, breakpoint, shortcut 등을 이용한 생산성 향상 방법을 배워보자 🛠

Size: 62.5 KB - Last synced: over 1 year ago - Pushed: over 2 years ago - Stars: 41 - Forks: 0