Ecosyste.ms: Repos

An open API service providing repository metadata for many open source software ecosystems.

GitHub topics: vitis-hls

rice-systems/lofreq-fpga

FPGA Acceleration for the LoFreq variant caller

Language: C - Size: 20.5 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 5 - Forks: 0

Binzakens/ET1_DT5-EFI-20231

This is an indie Electronic Fuel Injection System project that's been inherited from our sensẽi, Mr NQA. This project is a big bravo to the rest of my teammate, we've all been trying to do our best and we do.

Language: C - Size: 34.7 MB - Last synced: 5 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Language: TeX - Size: 191 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 1 - Forks: 0

esantosjr/FPGA-Function-Acceleration

Accelerating a simple function using an IP Block in the FPGA.

Language: Tcl - Size: 2.13 MB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 0 - Forks: 0

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Language: VHDL - Size: 46.9 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 2 - Forks: 1

SamsonAdem/HW_SW_Co_Design_FPGA

Hardware accelerator for Image processing in FPGA

Language: C++ - Size: 41.7 MB - Last synced: 4 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

autohdw/flames

Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)

Language: C++ - Size: 485 KB - Last synced: about 1 month ago - Pushed: 3 months ago - Stars: 2 - Forks: 0

brigio345/DaCH

DaCH: dataflow cache for high-level synthesis.

Language: C++ - Size: 11.1 MB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 9 - Forks: 3

vishalcseiitg/cs577-c-based-vlsi-design-project

Language: C - Size: 4.64 MB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

miltosmac/TCAD

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs

Language: C++ - Size: 246 KB - Last synced: over 1 year ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0

nodamushi/vitis_hls_bug_sample

Xilinx Vitis HLS 2022.2 bug sample

Language: C++ - Size: 4.88 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

ihsanalhafiz/SVM_Speech_Recognition_HLS

Language: VHDL - Size: 78 MB - Last synced: over 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

Related Keywords
vitis-hls 12 fpga 9 hls 6 vitis 4 xilinx 4 high-level-synthesis 3 vhdl 3 xilinx-fpga 2 cpp 2 vivado-hls 2 xilinx-vivado 2 modelsim 2 gtkwave 2 vlsi-design 2 vivado 2 hardware 1 hardwareaccelerator 1 image-processing 1 verilog 1 verilator 1 openram 1 openlane 1 netlist 1 bioinformatics 1 median-filter 1 vhdl-code 1 linear-algebra 1 cache 1 memory-management 1 kyber 1 postquantumcryptography 1 verilog-hdl 1 hardware-acceleration 1 hardware-description-language 1 stencil-computations 1 stencils 1 vlsi 1 speech-recognition 1 svm 1 bioinformatics-tool 1 counting-models 1 lofreq 1 poisson-binomial-distribution 1 probability-distribution 1 variant-calling 1 efi 1 systemc 1 zynq-7020 1 artix 1 artix-7 1 axi 1 axi-lite 1 axi-memory-mapped 1 axi-stream 1 basys3 1 embedded 1 vivado-ip-integrator 1 vivado-vitis 1 xilinx-hls 1 xilinx-vitis 1 fpga-soc 1 petalinux 1 zynq 1 asic 1 asic-design 1 chisel 1 chisel3 1