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GitHub topics: axi-memory-mapped

aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Language: TeX - Size: 191 KB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

Related Keywords
artix 1 artix-7 1 axi 1 axi-lite 1 axi-memory-mapped 1 axi-stream 1 basys3 1 embedded 1 fpga 1 hls 1 vitis 1 vitis-hls 1 vivado 1 vivado-ip-integrator 1 vivado-vitis 1 xilinx 1 xilinx-fpga 1 xilinx-hls 1 xilinx-vitis 1 xilinx-vivado 1