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GitHub topics: xilinx-vitis

triSYCL/sycl

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM

Language: C++ - Size: 1.37 GB - Last synced at: 21 days ago - Pushed at: 7 months ago - Stars: 118 - Forks: 21

TurakhiaLab/DP-HLS

HLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA

Language: C++ - Size: 111 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 7 - Forks: 1

FrankKesel/xilinx_tools

Xilinx Tools Tutorials

Language: C++ - Size: 36.7 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0

justin-marian/cla-16bits-adder

Carry-Lookahead 16-bits Adder (CLA16) computes sums by rapidly determining carry bits through parallel processing.

Language: C++ - Size: 807 KB - Last synced at: 21 days ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

harshonyou/TSP-on-FPGA

FPGA-based hardware-accelerated, parallelized, and highly optimized solution for solving the Travelling Salesperson Problem (TSP) using Xilinx Zynq-7000 on a Digilent Zybo Z7-10 board, featuring FreeRTOS for real-time task management.

Language: C - Size: 13.7 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 1

Prithvish04/reconfigurable_project

Canny edge detection in HLS

Language: Jupyter Notebook - Size: 10.1 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 0

efetunca/Zynq-7000-TFTP-Server

A TFTP server running on Zynq-7000

Language: C - Size: 3.83 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

ArioKian/Xilinx_Zynq7000_ZynqUltraScalePlus_PS_SdCardDrivers

Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.

Language: C - Size: 7.81 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Language: TeX - Size: 191 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

nodamushi/vivado_cmake_module

CMake for Xilinx Vivado/Vitis

Language: CMake - Size: 179 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0