GitHub topics: xilinx-hls
harshonyou/TSP-on-FPGA
FPGA-based hardware-accelerated, parallelized, and highly optimized solution for solving the Travelling Salesperson Problem (TSP) using Xilinx Zynq-7000 on a Digilent Zybo Z7-10 board, featuring FreeRTOS for real-time task management.
Language: C - Size: 13.7 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 1
matthiaskonrath/rc4-verilog
EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.
Language: C++ - Size: 169 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 7 - Forks: 0
aryan-programmer/axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
Language: TeX - Size: 191 KB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0
cescalara/zynq_ip_hls
Custom IP for the Mini-EUSO PDM-DP Zynq system
Language: C++ - Size: 7.81 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0
wurmmi/fm-radio
Master thesis project - Comparing a FM Radio implementation in VHDL versus high-level synthesis (HLS).
Language: VHDL - Size: 347 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0
nodamushi/vivado_cmake_module
CMake for Xilinx Vivado/Vitis
Language: CMake - Size: 179 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
cea-wind/hls_ldpc_dec
Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
Language: C++ - Size: 629 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 24 - Forks: 12
lastweek/fpga_icap_hls
HLS-based Xilinx ICAP3 Controller (tested with VCU108)
Language: Tcl - Size: 371 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 5 - Forks: 0
